Synopsys Webinar | Available On-Demand

For over a decade, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively verify the correctness of mathematical computations in these designs. Like CPUs and GPUs, AI processors are also datapath heavy with mathematical functions like addition, subtraction, matrix multiplication, and square root in its compute engines, making these designs a good fit for formal datapath validation. 

This Synopsys webinar will introduce the Synopsys ARC® NPX Neural Processing Unit (NPU) IP family of embedded AI processors and use of Synopsys VC Formal DPV to verify its datapath functions. The Synopsys ARC NPX6 processor supports the latest and most complex neural networks, such as CNN, RNN, and transformers, targeted for AI SoCs that are widely used in automotive, data center, high end gaming, next generation augmented reality, and surveillance. At the heart of the NPX6 neural network processor are convolution and tensor accelerators that are optimized to perform light speed computations. Correctness of these functional units are key to correct facial, audio, image processing and recognition which could have safety implications for automotive applications. We will explore Synopsys VC Formal DPV, the gold standard for datapath validation and signoff for the last 20 years, and how it is used to ensure correctness of the core algorithms of the ARC NPX6 processor’s compute engines. 


Listed below are the industry leaders scheduled to speak.

Neelabja Dutta Headshot

Neelabja Dutta

Sr. Manager, Applications Engineering


Neelabja Dutta is an Application Engineer in the Verification Group at Synopsys with 13+ years of EDA experience. He supports VC Formal Datapath Verification along with other VC Formal Apps and is based out of Mountain View, US.

Shuaiyu Jiang Headshot

Shuaiyu Jiang

Sr. ASIC Digital Design Engineer


Shuaiyu Jiang is a senior verification engineer for ARC processor team at Synopsys. He has more than 7 years of digital frontend verification experience. Currently, he is responsible for verification on Synopsys ARC NPX6 product.

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