HAPS®-70 Series

Physical Prototypes with the Highest Performance and Scalable Capacity

The HAPS-70 series is an easy-to-use and cost effective physical prototyping system. The HAPS-70 series enables early hardware/software integration and system-level validation at near-real-time run-rates, using at-speed, real-world interfaces.

HAPS-70 Features:

  • Modular system architecture, using Xilinx Virtex®-7 FPGAs, scales from 12 to 288 million ASIC gates to accommodate a range of design sizes, from individual IP blocks to processor sub-systems to complete SoCs. For system capacity ranging from 500k-4M ASIC gates, see the HAPS Developer eXpress (HAPS-DX) Series. For system capacity over 288 million ASIC gates, see the HAPS-80 Series.
  • Enhanced HapsTrak 3 I/O connector technology with high speed time-domain multiplexing delivers up to 3x performance improvement in data throughput over traditional pin multiplexing
  • System definition and bring-up utilities speed hardware assembly and ensure the prototype’s electro-mechanical integrity
  • Advanced power and cooling management
  • Design planning tools reduces time-to-prototype by 2-3 months streamlining the transition from block level IP validation to full system integration
  • High debug efficiency
  • Advanced use modes including hybrid prototyping
  • HAPS-70 systems are available in nine model variants, with capacities from 12 to 288 Million ASIC gates
  • Compatible with DesignWare IP Prototyping Kits

Benefits

High Performance

Performance is what has made the HAPS family the industry leader for a range of validation scenarios from independent IP blocks to full systems that integrate CPU subsystems.

HAPS-70 Intro video

Scalable Capacity

A modular hardware architecture along with the latest high-capacity FPGA technology allows for HAPS-70 series systems to scale from 12-288M ASIC gates.

Deep Visibility

Seamless debug visibility across FPGAs and a spectrum of trace storage options allow you to deep access and control with minimal impact to prototyping resources.

HAPS Deep Trace Debug video

Easy Bring-Up

IP and ASIC RTL migration technology from the industry's leading EDA vendor reduces your effort to deliver high-performance prototypes.

Connectivity Options

The benefits of stand-alone physical prototypes are clear, but co-simulation and transaction-based validation connectivity for HAPS-70 eases migration from an RTL simulation environment and enable a hybrid system that integrates SystemC/TLM models for the fastest SoC prototype bring-up ever.