Performance is what has made the HAPS family the industry leader for a range of validation scenarios from independent IP blocks to full systems that integrate CPU subsystems.
HAPS-70 Intro video
A modular hardware architecture along with the latest high-capacity FPGA technology allows for HAPS-70 series systems to scale from 12-288M ASIC gates.
Seamless debug visibility across FPGAs and a spectrum of trace storage options allow you to deep access and control with minimal impact to prototyping resources.
HAPS Deep Trace Debug video
IP and ASIC RTL migration technology from the industry's leading EDA vendor reduces your effort to deliver high-performance prototypes.
The benefits of stand-alone physical prototypes are clear, but co-simulation and transaction-based validation connectivity for HAPS-70 eases migration from an RTL simulation environment and enable a hybrid system that integrates SystemC/TLM models for the fastest SoC prototype bring-up ever.