Verdi Power-Aware Debug

Overview

Low power design techniques such as power gating, state retention, voltage islands and dynamic voltage/frequency scaling introduce new dimensions to SoC design which exponentially increase the complexity of low power verification and demand a specialized power-aware debug solution. Easy and efficient low power debug needs to have a unified view of the design and its power intent, and an understanding and awareness of the impact of power intent on the design, in order to identify potential design-killing bugs early in the design flow.

Synopsys’ Verdi® Power-Aware Debug enables the analysis of the impact of power intent on a design, and accelerates the debug of unexpected design behavior by automating the process of visualizing and tracing the source of power-related errors. In addition to Verdi’s core set of debug capabilities and views, Verdi Power-Aware Debug offers comprehensive design views, power intent visualization and debug automation capabilities to achieve a complete power-aware debug flow.