Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Webinar | On-Demand
This presentation details optimal recipes for comprehensive low-power verification with Formality equivalence checking. We will detail how Formality equivalence checking can help in efficiently tracing back UPF-related failures and achieve faster TAT in low-power equivalence signoff. The presentation also covers proper usage of Formality constraints in low-power verification. We will walk through several scenarios of low-power verification in which Formality constraints play an important role for successful low-power verification.
Listed below are the industry leaders scheduled to speak.
Associate Staff Engineer
India R&D Center (SSIR)
Ramanathan Lakshmanan is working as Associate Staff Engineer at Samsung Semiconductor Research (SSIR) since 2018. He is responsible for Synthesis, Equivalence checking, Low Power Checks & Post STA of various low power designs on technology nodes 5nm & 8nm. He has also worked on various complex issues in Equivalence checking across various projects in SSIR and has given constant support on Logic Equivalence as well as Low Power Equivalence signoff. He has helped in successful tapeouts of 3 SOCs at SSIR.
Ram holds a Bachelor of Engineering degree from Anna University , Chennai and has overall industry experience of 3.5 years.
Alphyn Stanley is working as a Senior Application Engineer at Synopsys. He started his career in Synopsys in 2018. His area of specialization is in Formality and Formality ECO. He has been handling Samsung India (SSIR) for Formality since 2019. He has helped in many Formality issues across various projects in SSIR. Other Synopsys accounts which he has worked/working are Broadcom, Cisco.Alphyn holds a Bachelor of Engineering degree in Electronics & Communication from Mahatma Gandhi University and Masters of Engineering degree in VLSI Design from Nation Institute of Technology Kurukshetra. He has an overall industry experience of 2.5 yrs.