During complex IP development, effort and time taken to perform a functional ECO is very high. It involves analysis and understanding of huge combinational and sequential blocks, and usually runs into multiple iterations if done manually. For example: the physical netlist multibit register mapping could be different and Synopsys IC Compiler II would not be able to perform the ECO straight away on the given ECO’d synthesized netlist, even though the RTL to synthesis equivalence is established using Synopsys Formality. In addition, using a manual approach to implement an ECO can be error prone and takes multiple Formal equivalence iterations to validate.
In this Synopsys webinar, presenters from Samsung and Synopsys will demonstrate an automated method that can be used to do a functional ECO for a fairly complex design with an ECO that may add sequential and combinational logics. Starting from an edited RTL to a patch implemented on an IC Compiler II PD netlist, the flow is completely automated and doesn’t need any manual intervention. This method significantly reduces the turnaround time to generate the functional ECO netlist. The only requirement to start is to have original RTL passing through Formality with the original netlist and have the new ECO’d RTL. This flow makes use of Synopsys Formality ECO.