Multiple voltage threshold (Vt) and channel length cells offer additional options for the tools as well as variants of these cell functions such as tapered cells that are optimized for minimal delays in typical processor critical paths. Having these critical path-efficient cells and computationally efficient cells, such as AOIs and OAIs, available from the standard cell library provider is critical, but so is having a design flow tuned to take advantage of these enhanced cell options. Additionally, high drive-strength variants of these cells must be designed with special layout considerations to effectively manage electromigration operating at GHz speeds.
To help the tools make the correct choices in selecting cells and minimize cycle time, it is often necessary to employ don’t_use lists to temporarily “hide” specific cells from the tools. Grouping multiple signals with similar constraints and loads can also make a major difference in synthesis efficiency. Attaining the absolute maximum performance out of a design requires the tools and flows to be pushed at different steps in the design flow (e.g., initial synthesis, incremental synthesis, clock tree synthesis, placement, routing, physical optimization). Optimization techniques can typically provide a 15-20% performance improvement.