Multi-bit flip-flops provide a set of additional flops that have been optimized for power and area with a minor tradeoff in performance and placement flexibility. The flops share a common clock pin, which decreases the overall clock loading of the N flops in the multi-bit flop cell, reduces area with a corresponding reduction in leakage, and reduces dynamic power on the clock tree significantly (up to 50% for a dual flop, more for quad or octal).
Multi-bit flip-flops are typically used in blocks that are not in the critical path of the highest chip operating frequency. They range from small, bus-oriented registers of SoC configuration data that are only clocked at power up, to major datapaths that are clocked every cycle and with a number of variants in between. SoC designers use the replacement ratio, measured by how many of the standard flops in the design can be replaced by their multi-bit equivalents and the resulting PPA improvements, to determine their overall chip power and area savings. The single-bit flip-flops to be replaced with multi-bit flip-flops must have the same function (clock edge, set/reset, and scan configuration).
Figure 7 shows a 32-bit processor being synthesized with a logic library for TSMC 28HPM (blue line) and again with the same library characterized to the TSMC 28HPC process (orange line), where you can see greater performance in less area. Including innovative cells such as those in the Synopsys High Performance Core Design Kit enables SoC designers to achieve smaller area for a given frequency and a higher top end frequency as seen in the dotted red and blue lines. Using the 28HPC+ process shifts this curve 15% to the right.