Six Logic Library Capabilities for Improved PPA on TSMC 28HPC+ Process
By Ken Brock, Product Marketing Manager, Synopsys
TSMC recently released its fourth major 28nm process into volume production—28HPC Plus (28HPC+). Millions of production wafers have come out of TSMC’s first two 28nm processes (the poly SiON 28LP and high-K Metal Gate 28HP/28HPL/28HPM). With 28HPC, TSMC had optimized the process for mobile and consumer devices’ need for balance between performance and cost and then developed 28HPC+ to achieve further performance improvement and leakage reduction. Using a combination of these new process technologies and high-quality standard cell logic libraries designed specifically for these processes, designers can achieve their performance, power and area goals while mitigating schedule risk.
This article describes six areas where designers can take advantage of these new processes with the latest logic library technology to optimize the performance, power and area of their SoCs.
- First, designers can improve SoC performance by using the global slow and fast (SSG, FFG) signoff corners enabled by TSMC’s tighter process controls with 28HPC/HPC + over 28LP/HP/HPL/HPM. The improved performance enables the use of lower drive (smaller) logic cells to close critical timing paths.
- Second, TSMC’s tighter process controls for the 28HPC process cut power consumption by reducing leakage by 20% in its corner models.
- Third, 28HPC+ achieves another 15% performance improvement and 25% leakage reduction.
- Fourth, both 28HPC and 28HPC+ reduce area, and therefore cost, as relaxed process rules enable library providers to deliver shorter cells with improved routability.
- Fifth, these same relaxed rules enable longer channel lengths to be drawn than could be drawn with the 28HPM process to reduce leakage power by up to 50% without use of expensive lithography-based gate biasing.
- Sixth, new logic library features introduced for the 28HPC process, such as multi-delay, multi-setup and multi-bit flip-flops (MBFF), help designers optimize their processor cores for performance and power.
The combination of innovative process technology and library design capabilities, along with the latest EDA tool innovations and flows, enable SoC designers to use their design skills to produce the highest performance, lowest cost designs consuming the lowest power.