Design metrics of performance, power, area, cost, and time-to-market (opportunity cost) have not changed since the inception of the IC industry.
Designing in FinFET broadens the design window. Operating voltage continues to scale down, significantly saving on dynamic and static power. Additionally, short channel effects are significantly reduced, decreasing the guard-banding needed to deal with variability, and performance continues to improve (compared to planar at an identical node). In fact, at very low power supply voltages, the performance advantage of the FinFET compared to its planar equivalent widens due to the superior gate control of the channel in the FinFET even at low voltages.
For memory designers, an added advantage of FinFET is the significantly lower retention voltage of FinFET-based SRAM compared to that of planar.
Given the new emerging metric of performance per unit power (Koomey’s law) one major design optimization alternative given the designer in FinFET vis-a-vis planar is greatly improved performance at the same power budget, or an equal performance at a much lower power budget. Quite a good place to be in.
One additional feature that eases the transition from designing in planar to designing in FinFET is the fact that the back-end of the process is essentially the same for both, and therefore a significant amount of the design flow associated with the back-end remains intact.