What is Glitch Power?

Definition

In electronics design, glitch refers to unnecessary signal transitions in a combinational circuit, while glitch power refers to the power consumed by glitches. The extra switching activity can lead to up to 40% of additional dynamic power consumption. The amount of glitch is proportional to the number of operations executed by the SoC, making glitch an important problem to address for artificial intelligence (AI) accelerators, where tiles are executing many operations. Since glitches can cause potential electro-mechanical (EM) and IR drop issues (even in the power grid), they should be suppressed by the designers or via implementation or ECO tools.

For designers, identifying glitches and revealing the extra power they consume requires special attention to cell delays and wire delays. Glitches occur if signal timing within the paths of a combinational circuit are imbalanced, causing a race condition. With accurate delay information, tools can capture these glitches and measure the power consumption caused by the extra switching activity.

Due to the huge number of operations performed when the AI algorithm is run on hardware, glitch power has become a critical consideration in terms of overall power consumption. Glitch power can represent up to 40% of the total power. In addition, due to the symmetric and replicated architecture of AI hardware, it is very important to identify the best possible micro-architecture for glitch early in the design cycle and, ideally, at the system level or RTL level. Reducing power for a highly replicated tile will lead to high-energy savings at the chip level. Typically, glitch power is computed very late in the flow when gate-level simulation with timing delays is available. This is too late to perform changes to the micro-architecture, take glitch power into consideration as part of the power budget during implementation, or perform specific ECOs to reduce glitch power. Hence, it is important to have in place a glitch power analysis solution along with delay-aware and glitch-aware vector generation early in the design cycle.

Glitch Power Figure 1

How does Glitch Power work?

Glitches occur if signal timing within the paths of a combinational circuit are imbalanced, causing a race condition. This generates an unwanted signal transition, causing additional dynamic power (potentially leading to up to 40% additional dynamic power). 

Glitch power can be measured at the gate level using a timing-aware solution and power analysis tool. New technologies are available to measure glitch power using RTL or 0 delay simulation as well. 

Glitch power is a cost function of implementation tool power optimizations. Implementation uses the additional toggle generated by glitch to make better decisions to suppress these glitches or place them in such a way that minimizes their impact on EMIR.

Glitch Power Figure 2: Example Circuit

What solutions does Synopsys offer?

Synopsys offers an end-to-end RTL-to-gate glitch power analysis and optimization solution. At RTL, PrimePower RTL can compute and report glitch per hierarchy so the instances with high glitch can be identified. It can also point to the RTL source line of code generating the highest level of glitch so designers can perform “what if?” analysis to reduce glitch power. This is very applicable for AI and ML hardware where the amount of glitch power is high due to the number of operations. Optimizing glitch power for a tile can lead to high power savings at the SoC level.

The PrimePower solution also offers delay-/glitch-aware vector generation using RTL simulation. The product can generate an SAIF with glitch annotation (IG and TG) and a delay-aware SAIF from an RTL simulation on any given netlist (synthesis output, CTS output, place-and-route output, etc.). The SAIF or FSDB can be used during implementation (Fusion Compiler) or ECO (PrimeECO design closure system, tweaker) to do glitch-aware optimizations.

Finally, PrimePower gate-level power analysis and golden power signoff can perform glitch power analysis using 0 delay gate-level simulation or timing-aware simulation correlating closely to SPICE power numbers.

Glitch Power Figure 3: Power Analysis