For designers, identifying glitches and revealing the extra power they consume requires special attention to cell delays and wire delays. Glitches occur if signal timing within the paths of a combinational circuit are imbalanced, causing a race condition. With accurate delay information, tools can capture these glitches and measure the power consumption caused by the extra switching activity.
Due to the huge number of operations performed when the AI algorithm is run on hardware, glitch power has become a critical consideration in terms of overall power consumption. Glitch power can represent up to 40% of the total power. In addition, due to the symmetric and replicated architecture of AI hardware, it is very important to identify the best possible micro-architecture for glitch early in the design cycle and, ideally, at the system level or RTL level. Reducing power for a highly replicated tile will lead to high-energy savings at the chip level. Typically, glitch power is computed very late in the flow when gate-level simulation with timing delays is available. This is too late to perform changes to the micro-architecture, take glitch power into consideration as part of the power budget during implementation, or perform specific ECOs to reduce glitch power. Hence, it is important to have in place a glitch power analysis solution along with delay-aware and glitch-aware vector generation early in the design cycle.