Mastering AI Chip Complexity
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Fast and Accurate Functional ECO Implementation and Verification Using FM ECO and Formality
Date: Jul 09, 2025 | 10:00 AM PST
Featured Speakers:
- Sabarna Choudhury, Staff Engineer, Qualcomm
- Makarand Patil, Senior Director R&D, Synopsys
Discover how to streamline your design modification and verification processes with Synopsys FM ECO and Formality. This Synopsys webinar will provide valuable insights into accelerating product development while maintaining design integrity. Here's why you should attend:
- Master Functional ECOs: Learn how to implement design changes quickly and accurately without restarting the entire design cycle.
- Optimize Your Workflow: Explore how Synopsys FM ECO generates precise patches for complex logic modifications, saving time and effort.
- Accelerate Verification: Understand how Synopsys Formality reduces verification cycles with its distributed processing mechanism for faster equivalence checking.
- Achieve Faster Design Closure: Gain strategies to minimize disruption to your design flow and ensure reliable results under tight timeframes.
Don't miss this opportunity to enhance your ECO implementation and verification expertise!
Register Now
Featured Speakers
Sabarna Choudhury
Staff Engineer, Qualcomm
Sabarna Choudhury leads the Formal Verification and Functional ECO Implementation activities for cutting-edge GPU projects. He has 6 years of ASIC design experience and currently has experience in RTL-GDS flows including synthesis, equivalence checking, and functional ECOs for signoff. Sabarna has a master’s degree from the University of Minnesota, Twin Cities, USA and Bachelor’s degree from West Bengal University of Technology, India.
Makarand Patil
Senior Director R&D, Synopsys
Makarand Patil (Miki) is the R&D manager for Synopsys Formality and Formality ECO products. He has over 20 years of experience in logic equivalence checking technologies spanning various areas of equivalence checking, such as RTL-Gate verification flows, solver engines, front-end language support, functional ECO, datapath optimizations, and UPF aware verification flows. Makarand holds a master’s degree in computer engineering from University of Kansas and a bachelor’s degree from Mumbai University.