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Accelerated Optimization with IC Compiler II
Ultimately, the challenge of physical optimization is to provide design convergence and closure as a design moves from the logical realm into the physical world.
Technology scaling, in as much as it drives the density demands required of Moore’s law, comes with growing challenges of increasing interconnect delay. As we transitioned through maturing nodes, cell delay was the dominant factor. However, as wire cross sections have shrunk with each new node, the associated wire resistivity has grown exponentially.
Therefore, today’s designs are becoming increasingly “buffer heavy.” It has been reported that in newer technologies, it is not unusual to see over 25% of all cells merely existing to move signals around the device in a timely manner. This trend is not expected to slow down even with the introduction of higher power devices such as FinFETs; their higher drive being offset by more highly resistive materials required for multiple patterning, as well as larger dies—thus longer nets—for growing designs.