Synopsys White Paper

Advanced Design Planning in IC Compiler II

Gordon Moore, through his often touted 1965 ‘law’, bravely set out a prediction of economies of scale and what that could augur for a successful integrated circuit (IC) industry. Through continued node scaling, the industry has managed to closely track his prediction–albeit with a few bumps along the way–to deliver on that vision.
 

As we continue to rush to these latest nodes with the aim of packing more and more devices into smaller and smaller spaces, a growing challenge is commanding more attention–that of how to manage the design capacity required at these newer nodes. Where designs were once measured in thousands, then millions of active devices, we have already traversed the billions of devices threshold. There is no sign of abatement and we can see a transition through the giga-scale era into much more in the near future.