With increasing manufacturing complexity at advanced technology nodes and shrinking design schedules, physical verification turnaround time is critical to deliver tape-outs on schedule.
On March 22 2018, Synopsys hosted an IC Validator panel at SNUG in Santa Clara, CA. At this event, foundry and market leading technologists discussed the verification challenges designers face today, and the technology required for a convergent and efficient physical signoff flow delivering the fastest path to production silicon.
Senior Manager, Applications Engineering, Synopsys
Senior Director, Advanced Technology Group, NVIDIA
Principal Engineer, Juniper Networks
Senior CAD Engineer, Socionext