Cloud native EDA tools & pre-optimized hardware platforms
By: Lakshmi Jain, Product Marketing Manager and Wei-Yu Ma, Technical Marketing Manager for IO Libraries, Synopsys
There is a rapidly growing demand for non-volatile Flash memories in the Automotive, AI, and IoT markets for applications that require a fast reading of the massive code base and timely response on the system power-up. Embedded systems utilize non-volatile memory to store boot code, application code/data, AI weights, calibration parameters, diagnostic data, configuration parameters, and other data that persist when the system is powered down. Today, Flash memories fulfil this role in most embedded systems. However, advancements in Flash technology cannot keep up with advances in standard logic technology; therefore, standard logic technology and Flash cannot be mixed on the same die in the most advanced processes.
Systems using SoCs designed in advanced processes generally rely on external Flash devices that use NOR/NAND Flash memory technology for non-volatile storage. NOR Flash memory offers many benefits for device manufacturers and consumers, such as faster reading, low power consumption, and smaller area. In contrast, NAND Flash memories are ideal for applications such as data storage, where higher memory capacity and faster write and erase operations are required.
In this article, we will discuss:
Figure 1: xSPI is everywhere
Table 1: Comparison of the SPI growth
Modern NOR Flash devices offer fast initialization time and high bandwidth to minimize boot-up time. The bandwidth can reach 400 MB/s when used with the JEDEC xSPI interface in the Octal or HyperBus bus protocol. Looking at a specific example, a typical U-boot sized between 1 MB to 2 MB with a read bandwidth of 400 MB/s would translate to 5 ms read time, plus a maximum 300 µs device initialization time for the NOR Flash. Compare this to eMMC initialization, which would be ~100 ms and UFS ~50 ms. In addition, if the processor runs XIP directly on NOR Flash, the number of pins is significantly reduced. This results in savings of two to four layers of PCB design, decreasing the overall system cost. Therefore, xSPI is the obvious choice for low-density NAND or NOR Flash memories, as well as PSRAM, which is preferred as a low-cost replacement for internal cache memories against expensive SRAMs.
For designers planning to embed Flash memories in their SoCs, Synopsys provides a comprehensive xSPI platform solution (Figure 2) that enables them to reduce the SoC development cycle. The solution includes:
The Synopsys fully verified xSPI hardened PHY and Controller offering is complemented by an integration guideline. Additionally, Synopsys performs comprehensive interoperability verification to reduce designers’ SoC implementation effort. This enables seamless integration with devices and peripherals that support these standards.
Figure 2: Synopsys xSPI Platform Solution