Synopsys Specialty I/O library IP provides designers with the input/output operation, functionality and reliability required for SoCs targeting mobile, automotive, and high-performance computing (HPC) applications. Available in many foundries and process technologies from 3nm to 22nm, the specialty I/O library supports multiple voltages and a complete set of support cells (supply, corner spacers, diode breakers, terminators). Synopsys Specialty I/Os meet critical power, performance, area (PPA), and reliability requirements for standards including LVDS, sLVDS, eMMC, I2C and I3C.
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A few typical LVDS I/O applications are in display monitors, printers, high-speed clock transfers, and high-speed SERDES. Synopsys LVDS I/O library is used to build an LVDS-based interface for high-speed interconnect applications. This library is designed to optimize I/O performance with a core voltage of 0.75 V and supports an I/O supply voltage of 1.2V/1.5 V. The library contains a transmitter, a receiver, and a bandgap reference circuit that is used to supply the current reference for the transmitter/receiver. The LVDS I/O library is compatible with the IEEE standard 1596.3-1996 and TIA/EIA - 644 -A. Key Features are:
Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters and microcontrollers on the same bus. It is designed for higher I/O voltage supply with support for low core voltage and includes fail-safe and fail-tolerance options. The following operating modes are supported:
Key features are:
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can be controlled by one I3C primary device at a time. It offers backward compatibility with I2C legacy devices, is designed for high I/O voltage domains and supports low-core voltage domains. The I3C incorporates the Schmitt-Trigger function, supports I2C Legacy Fast Mode and FM+ Mode, and includes HBM and CDM ESD protection. We provide an interoperable validated I3C I/O solution with our in-house Synopsys I3C controllers. The library supports independent power sequencing with the support of a power management cell from our base libraries. The Synopsys I3C I/O specifications align with the latest JEDEC standards and support:
Key Features are:
Synopsys SD/eMMC PHY, SDIO, eMMC I/O: Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations. It includes an optional digi logic circuitry which is required for high-speed operations. It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards. The fey features are:
Synopsys Programmable Crystal Oscillator: Synopsys offers low jitter Programmable Crystal Oscillator that supports 5 MHz to 50 MHz, with optimized design to reduce jitter and to support wide operation. In addition, the bypass mode is supported with a maximum frequency of 50 MHz. Key features are:
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