Synopsys Specialty IO library and PHY provide designers with the input/output operation, functionality and reliability required for SoCs targeting mobile, automotive, and high-performance computing (HPC) applications. Available in many foundries and process technologies from 3nm to 22nm, the specialty IO library supports multiple voltages and a complete set of support cells (supply, corner spacers, diode breakers, terminators). Synopsys Specialty IOs meet critical power, performance, area (PPA), and reliability requirements for standards including LVDS, sLVDS, eMMC, I2C, I3C, xSPI, and High-Speed Test IO.
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Synopsys Low Voltage Differential Signaling (LVDS) IO library is a high-frequency interface that uses differential signals for data transmission. A few typical LVDS IO applications are in display monitors, printers, high-speed clock transfers, and high-speed SERDES. Synopsys LVDS IO library is used to build an LVDS-based interface for high-speed interconnect applications. This library is designed to optimize IO performance with a core voltage of 0.75 V and supports an IO supply voltage of 1.2V/1.5 V. The library contains a transmitter, a receiver, and a bandgap reference circuit that is used to supply the current reference for the transmitter/receiver. The LVDS IO library is compatible with the IEEE standard 1596.3-1996 and TIA/EIA - 644 -A. Key Features are:
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Synopsys Inter-Integrated Circuit (I2C) IO library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters and microcontrollers on the same bus. It is designed for higher IO voltage supply with support for low core voltage and includes fail-safe and fail-tolerance options. The following operating modes are supported:
Key features are:
Synopsys I3C IO library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can be controlled by one I3C primary device at a time. It offers backward compatibility with I2C legacy devices, is designed for high IO voltage domains and supports low-core voltage domains. The I3C incorporates the Schmitt-Trigger function, supports I2C Legacy Fast Mode and FM+ Mode, and includes HBM and CDM ESD protection. We provide an interoperable validated I3C IO solution with our in-house Synopsys I3C controllers. The library supports independent power sequencing with the support of a power management cell from our base libraries. The Synopsys I3C IO specifications align with the latest JEDEC standards and support:
Key Features are:
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Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations. It includes an optional digi logic circuitry which is required for high-speed operations. It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards. The fey features are:
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Synopsys offers low jitter Programmable Crystal Oscillator that supports 5 MHz to 50 MHz, with optimized design to reduce jitter and to support wide operation. In addition, the bypass mode is supported with a maximum frequency of 50 MHz. Key features are:
xSPI PHY, xSPI IO
Fully Hardened xSPI PHY Solution
Integrated (Readymade) and area-optimized
Consistent delay line granularity/resolution across PVT
Electrically compliant drivers
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