Understanding the MIPI M-PHY
By Sérgio Silva, Project Director, DesignWare MIPI M-PHY IP and Hezi Saar, Staff Product Marketing Manager, DesignWare MIPI PHY and Controller IP
Consumers today demand higher performance, feature-rich applications, and higher quality multimedia content in their mobile devices. To design these high-performance devices, designers need to contend with pin count and channel limitations (including the physical dimensions, cost, and package reliability) as well as bandwidth bottlenecks. At the same time, battery operated mobile devices strive for very low power consumption in active and idle periods with quick entry and exit times.
The high-speed MIPI® M-PHY is tailored for mobile systems and is becoming a popular physical layer solution. The M-PHY is designed to accommodate the intermittent nature of inter-chip communications and employs burst operation to toggle between data transmission and power saving states, effectively reducing power consumption.
As the M-PHY gains in popularity, standards bodies such as PCI-SIG and USB-IF are developing digital controllers that interoperate seamlessly with the M-PHY. Designers familiar with PCI-SIG’s PCI Express and USB-IF’s USB 3.0 need to understand the basics of the MIPI M-PHY for success using the emerging SSIC protocol, as do any designers working on low-power consumer and mobile system-on-chips (SoCs).