Sensor technology leading to sensor fusion

The devices we use every day have raised the bar on consumer expectations for reading and interpreting environmental conditions. In the car, sensors help avoid collisions by alerting the driver to traffic in the blind spot before changing lanes, or efficiently control wiper blades by detecting rain on the windshield. In the home, video games can be controlled by body movement, and touch screens are ubiquitous interfaces on appliances, computers, and phones. On the go, we rely on sensors in our mobile devices to help us navigate, interpret weather conditions, and determine proximity.

The increasing sophistication of sensor technology has led to multiple sensors being combined to provide higher order functions. For example, geo-fencing combines movement, gesture, and geo-location sensors to customize a mobile device’s user experience for that particular location. This combination of various sensor elements (analog and digital) is known as sensor fusion.

The number of systems incorporating sensor fusion technology is exploding as semiconductor suppliers push to integrate sensor interfaces into their SoC offerings. According to Semico Research and shown in Figure 1, the number of systems incorporating sensor fusion is predicted to grow from 400M units in 2012 to over 2.5B units in 2016 – an annual growth rate of almost 60%.

The evolution of sensor integration

As is common across all SoC functions, increased integration of sensor control provides gains in overall performance, while reducing software footprint, silicon area, and power consumption.

At the most basic level of sensor control, an analog signal is converted to a digital signal that can be used by digital control logic (such as a microcontroller). Traditionally, this was handled by a set of discrete components that converted and filtered the signal that was then transmitted by a digital peripheral to another device.

As systems evolve, more of the discrete functionality is incorporated into processor-based SoCs, as shown in Figure 2. This functionality includes converting the analog signals to digital as well as coalescing the various sensor sources (creating sensor fusion). The SoCs also provide signal processing functionality and “core” functionality such as floating point and fixed-point arithmetic and provisions for custom functions which are often handled by on-chip accelerators.

Optimized Sensor Subsystem

Within the sensor subsystem, the advantages of increased integration can differentiate a silicon vendor’s device. A typical “integrated” solution today involves incorporating the sensor interfaces into a microcontroller-like architecture. This architecture (shown in Figure 3) generally includes a typical CPU, connected through an on-chip bus to peripheral interfaces (ADC and DAC) as well as on-chip memories (ROM, RAM, Flash). The processor is connected to a standard bus (typically AMBA based) and all of the peripherals are connected to the bus. Transactions between the processor and peripherals take three to seven clocks or more due to bus latency and traffic on the bus. This is very inefficient in terms of performance and power consumption.

The DesignWare Sensor Subsystem offers three distinct advantages to help ease integration effort while reducing on-chip latency and power consumption compared to typical bus-based systems.

1. Closely coupled memories (I-CCM / D-CCM):
   The ARC EM4 core provides an option to integrate tightly coupled memories for both instructions and data to reduce access times going across the AHB bus to ROM and RAM in a bus-based topology.
2. Tightly integrated I/O:
   Starting from existing bus-based I/O peripheral, an ARC processor implementation can eliminate the interface to on-chip bus by replacing load/store instructions to the I/O peripheral with register move instructions. The peripheral block registers are mapped using ARC’s auxiliary bus.
   This implementation effectively pulls the I/O peripheral interface functionality into the CPU complex, eliminating the buses and bridges. Tightly coupling the I/O in this manner also enables single cycle access to all peripheral functions – increasing performance while reducing power consumption and die area to use fewer gates.
3. Customizable hardware / custom instructions:
   ARC processors support an implementation to add any combination of hardware extensions to the core: CPU extension registers, auxiliary extension registers, or memory mapped blocks. Designers can add 32-bit custom instructions as well. The hardware extensions are added with standard code (either as Verilog or C) and are accessed and run using special (custom defined) instructions.

In addition to these ARC EM4 features, Synopsys’ Sensor Subsystem (Figure 5) provides an additional level of hardware integration to accelerate standard DSP sensor application functions. These functions include complex math functions (square root), filtering (FIR, IIR, correlation), matrix/vector operations, and interpolation. Implementing the DSP functions in hardware reduces the memory footprint by replacing application software code with hardware accelerator instructions.

Improving area, power, and performance

Integrating the ARC EM4 processor with sensor interfaces and DSP hardware accelerators provides significant improvements in area, power and performance.

Typical sensor implementations yield area savings on the order of 40-60% over normal bus-based implementations, as shown in Figure 6. These sensor implementations can include:

• Intelligent sensors (processing added to analog sensor)
• Combination sensors
• Sensor hubs (aggregation of multiple sensors within a device)

Filtering and cyclical redundancy checking (CRC) are common features in a sensor control application. To analyze the performance and die size changes, analysis was completed using the DesignWare Sensor Subsystem for a Finite Impulse Response (FIR) filter as well as a fixed polynomial CRC case. These features can be optimized for software only, or implemented with a combination of software and multiply-accumulate hardware.

As seen in Tables 1 and 2, implementing the FIR functionality in hardware (using an additional accelerator) will increase the overall area by ~1260 gates (NAND2 equivalent gates), but will reduce the clock cycle count 6x and reduce the code footprint by about 33%. For the CRC case, a 25x improvement in cycle count and 6x area improvement is achieved.

Summary

As sensor technology becomes ubiquitous, the number of consumer-based systems incorporating sensor technology is exploding. Typical sensor-driven applications such as those on mobile devices and in automotive markets require a higher level of sensor integration, which is achieved by designing the sensors into the SoC. As semiconductor suppliers increasingly integrate sensor interfaces into their SoC offerings, the market demands higher performance while reducing area and power consumption.

Synopsys’ Sensor Subsystem combines the unique capabilities of the ARC EM4 CPU with sensor and actuator interfaces and hardware accelerators for sensor control to provide significant gains in overall performance, while reducing software footprint, silicon area and power in embedded systems.