It may be necessary to use a placement or location command to be sure to get the correct flip-flop located into the I/O pad. The hierarchical name for this flip-flop will vary with your design, and perhaps with the configuration of your USB 3.0 core. However here is an example of a Xilinx placement command:
inst_port.U_DWC_usb3_pwrm_prt/U_DWC_usb3_pwrm_u3piu/phy_pipe3_rx_stage1" LOC = ILOGIC_X0Y196;
Another item associated with the interface is the clock phase, which affects both the USB 3.0 pipe interface and the USB 2.0 ULPI. Different FPGA builds can require modifying the clock phase to accommodate timing changes from build to build due to placement and routing variations. Modifying the clock phase is accomplished by using the Xilinx Mixed Mode Clock Manager (MMCM) to phase shift the clock to correctly sample the input. This can require some experimentation to set correctly, but once the correct setting is found, it typically stays constant for subsequent builds. This phase shift can be implemented using the FPGA_EDITOR for Xilinx after the build is placed and routed, so experimental attempts can be made quickly.
2. USB Clocking Solutions with Xilinx FPGAs
Clock multiplexing is common in the DesignWare USB 3.0 controller to accommodate the different operational modes. This is implemented by utilizing the global buffer multiplexers (BUFGCTRL) provided in the Xilinx FPGA. However if the Xilinx tool is allowed to select the BUFGs, it is possible to have excessive clock insertion delays between domains. This causes the tool to fix large hold times, which can result in long run times and sometimes affect the quality-of-results. Virtex 6 offers ‘fast track’ connections between the BUFGs, which help alleviate large insertion delays. This involves placing the BUFGs adjacent to each other to utilize the ‘fast tracks’. An example of this is shown in Figure 2.