Multicore Design Using ASIPs: Blending Performance and Efficiency with Programmability
By Markus Willems, Sr. Product Marketing Manager, Processor Solutions, Synopsys
In the early 2000s, analysts warned about a looming complexity crisis in ASIC design. It was forecast that by 2006, designers would no longer be able to make effective use of the abundant logic-gate counts promised by new process technology nodes of 90 nanometer (nm) and beyond. Yet new generations of SoCs have emerged for all kinds of systems, from wireless communicators over multimedia devices to automotive systems. The industry has responded to the complexity threat by an increased use of semiconductor IP and programmable processor cores.
The traditional SoC approach saw the use of standard microcontrollers and eventually DSPs, while offloading performance or power-critical functions into specialized fixed-function accelerators. Moving such functions into these accelerators comes with a heavy cost: loss of programmability, and therefore loss of flexibility after manufacture. This is intolerable with advanced process technology nodes, where high mask costs necessitate the reuse of silicon in multiple products and product generations to expand the revenue lifetime of an SoC.
As a result, there is a trend towards the use of heterogeneous multicore SoCs, which feature a range of very specialized processor cores with architectures and instruction-sets optimized for a certain application: application-specific instruction-set processors (ASIPs). ASIPs fill the architectural spectrum between general-purpose programmable processors and dedicated hardware or fixed-function cores by enabling designers to effectively combine high flexibility through software programmability with high performance efficiency (high throughput and low energy consumption). Figure 1 illustrates this concept for wireless baseband chips, where multi-ASIP cores enable software defined radio.