By Dr. Antonio Salazar, Senior Prototyping R&D Engineer, Synopsys
Hardware/software co-development traditionally suffers from long iteration cycles due to inherit dependencies among separate functional and implementation specifications, protocols and engineering teams. Frequent RTL drops and debugging iterations are a few of the bottlenecks that impede the fast progression of hardware/software co-design, in particular when considering scenarios of IP integration in SoC designs.
To accelerate time-to-market, designers must make compromises in features, testing, cost/expenses, and sometimes even quality. This is particularly true when considering SoC environments that require multiple IP cores along with legacy code, which will require interfaces on both sides of the hardware/software coin. Although IP can solve a number of issues and save considerable time, energy and effort, it can be a black box of knowledge that requires a steep learning curve. While configurability and flexibility are key aspects of well-designed IP, these features can introduce complexity and challenges. Some designers need hardware-level configurability to achieve an optimized design, while others require more self-managed hardware that raises the task to a software level. In either case, designers may face a never-ending sea of databooks, user manuals, application notes, and more.
The path to SoC software design is not like the electronic kits that are sold at electronic consumer websites, but it should be closer to that experience. All SoCs are composed of similar blocks such as a CPU, a communication bus, memory controller, I2C, SPI, or similar. So then why, if designers have connected similar blocks hundreds of time before, should basic design be so difficult? Prototyping an ASIC, which arguably is mostly composed of legacy RTL and IP blocks should not take so much time and effort, nor should iterations be so laborious.
In reality, designs are never as similar to the past one as one would hope. Standards are updated, protocols change, new requirements appear, consumer tendencies shift the priorities, etc., and time-to-market pressures demand faster design.
The iteration flow has a very real effect on a product’s bottom line. After an idea for a product is proposed, specifications are generated and designers figure out the logic required to comply with the latest trends and standard of communication. This process consumes valuable design time while time-to-market pressures remain. Prototyping environments not only provide the means for accelerated hardware validation by permitting designers to address issues early in the production cycle, they can also serve as a feature and configuration exploration environment that ensures a fast iteration flow.