- All Products
- Software Integrity
- Semiconductor IP
- Verification
- Design
- Silicon Engineering
- Application Security Services
- Dynamic Analysis (DAST)
- Mobile Application Security
- Penetration Testing
- Managed Static Analysis
- All Services
- Software Security
- Silicon Design
- Community
- About Us
< All Products
< All Products
< All Products
< All Products
< All Products
< All Products
< overview
All Products
+ Software Integrity + Semiconductor IP + Verification + Design + Silicon Engineering + Optical Solutions< Software Integrity
< Software Integrity
Application Security Services
Dynamic Analysis (DAST) Mobile Application Security Penetration Testing Managed Static Analysis< Software Integrity
< Software Integrity
< Software Integrity
Blog
< Software Integrity
Support
< overview
Software Integrity
+ Application Security Products + Application Security Services + Resources + Training & Education Blog Support< Semiconductor IP
< Semiconductor IP
Memories & Libraries
Logic Libraries Memory Compliers Duet Packages HPC Design Kit Embedded Test & Repair Non-Volatile Memory< Semiconductor IP
< Semiconductor IP
Processor Solutions
ARC Processors Embedded Vision Processors Development Tools Operating Systems Ecosystems ASIP Tools< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< overview
< Verification
< Verification
< Verification
< Design
< Design
< Design
< overview
< Silicon Engineering
< overview
< main menu
< Solutions
< Solutions
Industry Solutions
Automotive Cloud Computing Financial Services Industrial Controls Systems Healthcare Mobile Devices< Solutions
< overview
< All Services
< All Services
< All Services
< overview
< Software Security
Software Security Professional Services
Embedded Software Testing Insider Threat Detection Red Teaming Secure Coding Guidelines Software Architecture & Design Thick Client Testing< Software Security
Managed Services
< Software Security
Program Development & Design
Maturity Model (BSIMM) Maturity Action Plan (MAP) Policies & Standards Security Metrics Software Security-in-a-Box< Software Security
< Software Security
Support
< overview
< Silicon Design
< Silicon Design
< Silicon Design
< Silicon Design
< main menu
< Community
Community
Community Overview< Community
< Community
< Community
Interoperability
ARC Access HAPS Connect HSPICE Integrator In-Sync System-Level Catalyst TAP-in VC Apps Access< Community
< Community
< Community
< overview
Community
+ Community + SNUG + Partners + Interoperability + Academic Programs + Company Blogs + BSIMM< About Us
< About Us
< About Us
< About Us
< About Us
DesignWare Technical Bulletin
Ethernet QoS v4.0 Controller for 802.1 Compliant Networks
By John Swanson, Senior Marketing Manager, Synopsys, Inc.
As designers look to their next-generation network designs, they are faced with new challenges for products that incorporate the common Ethernet interface. Not only is the Ethernet standard moving into faster network communications, as seen by the move to 40G and 100G, but it is also being updated to support streaming audio and video applications over Local Area Networks (LANs).
In 2008 and 2009, we saw several IEEE specification updates either ratified or advanced to solid draft versions that are targeted at improving networking systems’ Quality of Service (QoS). Incorporating these updates into new consumer products is critical to satisfying consumers’ growing throughput demands. The work being done by the 802.1 Audio Video Bridging (AVB) work groups enables designers to more easily incorporate Ethernet QoS into not only Ethernet networks, but into all 802-compliant networks, and which gives consumers a wider range of options that support streaming audio and video in their home and automotive systems.
Synopsys released the first generation DesignWare® Ethernet QoS controller IP in 2010. Designers have used this core in both consumer and automotive applications for several years. The new Ethernet QoS v4.0 controller IP enhances Ethernet performance by significantly increasing the number of transmit and receive channels as well as adding support for new features in TCP/IP offloading and data center bridging.
Designers can select between four different architectures to integrate the Ethernet QoS v4.0 controller IP into their system-on-chip (SoC) designs, just as they could with the previous version of the IP. These are simple configuration options invoked from coreConsultant, providing designers with a flexible system design and optimized RTL for their specific designs. Each configuration can support 10/100/1G Ethernet speeds. The four base configurations are:
- Media access controller (MAC)
- MAC with memory controller
- MAC direct memory access (DMA)
- MAC with an AMBA system side interface
Figure 1: DesignWare Ethernet QoS v4.0 Controller IP
The Ethernet QoS v4.0 controller IP supports all of the features in the existing Ethernet QoS controller IP and adds:
- Scalability with support for up to eight transmit AVB channels and eight receive AVB channels
- Separate FIFO memory and controllers for every Tx or Rx channels added with a new architecture allowing implementation in a single memory with programmable size for each queue
- New architecture for multi-channel DMA (up to eight channels) that interfaces with multiple queues with a single RAM FIFO
- TCP/IP segmentation offload features including
- Stateless offloading
- Max TCP packet payload segmented to 256 KB
- Programmable maximum segment size (MSS) per packet
- The same header as the parent TCP packet
- Context descriptor sequence
- Option for external TSO memory for TCP/IP headers
- Checksum offloading engine (COE), which is essential for TSO
In addition, configuration options in the Ethernet QoS v4.0 controller IP include new data center bridging features. The initial release of the IP supports:
- Separate channels or queues for DCB data transfer in 100 Mbps and 1000 Mbps modes
- Up to eight queues on the Tx and Rx paths for DCB traffic
- Following IEEE 802.1-Qaz-2011 specified Enhanced Transmission Selection (ETS) algorithms for the Tx queues
- Following IEEE 802.1Qbb-2011 specified Priority-based Flow Control
- Common memory for all selected Tx or Rx queues. The system-side interface (AHB, AXI, or native) remains the same
- Programmable control to route received VLAN tagged non-AV packets to channels or queues
As in the first generation, the Ethernet QoS v4.0 controller IP supports all standard PHY interfaces, including:
- Gigabit Media Independent Interface (GMII)
- Media Independent Interface (MII)
- Reduced GMII (RGMII)
- Serial GMII (SGMII)
- Ten Bit Interface (TBI)
- Reduced MII (RMII)
- Serial MII (SMII)
- Reduced TBI (RTBI)
- Reverse MII (RevMII)
In addition to the new RTL design, Synopsys has expanded driver support options through a partnership with Vayavya Labs. Vayavya Labs was founded in 2006 with patented device driver generation technology and brings extensive domain expertise in embedded software design, development, and testing. With the Synopsys Ethernet QoS v4.0 controller IP, designers receive the base driver that provides the basic network driver tested on a Linux 3.0 system. This base driver includes a single DMA channel with ring mode descriptor support. Designers using Synopsys’ Ethernet QoS v4.0 controller IP can also license a comprehensive driver from Vayavya Labs that provides additional features:
- Multi-channel DMA
- VLAN tag detection (IEEE 802.1Q)
- Energy Efficient Ethernet (IEEE 802.3az-2010)
- TCP segmentation offloading
- Audio video bridging (IEEE 802.1Qav-2009 and IEEE 802.1AS-2011)
- Large receive offloading
- Jumbo frame handling
- Precision time protocol (IEEE 1588-2008)
Synopsys and Vayavya Labs jointly developed and validated this new comprehensive driver using a HAPS FPGA-based prototyping solution running the Ethernet QoS v4.0 RTL with the new software drivers using a Linux based system.
The DesignWare Ethernet digital IP is packaged as a .run file. Designers use the Synopsys coreConsultant tool to configure, synthesize, simulate, and verify the IP configuration. The Ethernet QoS v4.0 controller IP also includes:
- Configured Verilog RTL source code
- Verilog test suite that integrates the device-under-test (DUT) models
- Synopsys Ethernet Verification IP that can be reused in your Verilog, VHDL, or Vera Verification environment
- Synthesis scripts for Synopsys Design Compiler and Synplify Pro
- Regression scripts for Synopsys VCS, ModelSim, and NC-Verilog simulators
- Leda checker rules used for linting and example report
- Support for creating gate-level DUT models using a GTECH library
In summary, the DesignWare Ethernet QoS v4.0 controller IP is designed for today’s challenging Ethernet systems in multiple application spaces. It offers a smaller area for AVB and advanced features supporting TCP/IP offloading, memory management, and data center bridging. The new software driver partnership with Vayavya Labs enables Synopsys to continue to provide the best-in-class drivers that IP designers need for their applications. The IP is available today. For more information, please contact us.
Events