Cloud native EDA tools & pre-optimized hardware platforms
Vadhiraj Sankaranarayanan, Sr. Technical Marketing Manager, Synopsys
Today, Dual Data Rate (DDR) Synchronous Dynamic Random-Access Memory (SDRAM or simply DRAM) technology is the de facto memory used in almost all applications, from high-performance enterprise and data-center to power-/area-sensitive mobile applications. This is due to DDR’s high density with a simplistic architecture using a capacitor as a storage element, low latency at a high performance, almost infinite access endurance, and low-power consumption. JEDEC has defined and developed three DDR standards - standard DDR, mobile DDR, and graphic DDR - to help designers meet their memory requirements. The latest generation in the standard DDR category, DDR5, is currently under development at JEDEC, and according to Wikipedia, “as of September 2019, the standard is still being finalized by JEDEC, and is expected to be published in 2020.” DDR5 will support a higher data rate (up to 6400 Mb/s) at a lower I/O Voltage (1.1V) and a higher density (based on 16Gb DRAM dies) than DDR4. DDR5 DRAMs and dual-inline memory modules (DIMMs) are expected to hit the market in 2020. This article outlines several key features of DDR5 DRAMs that designers can deploy in their system-on-chips (SoCs) for servers, cloud computing, networking, laptop, desktop, and consumer applications.
Standard DDR DRAMs, providing high-density and high-performance, are available in various types and form factors and support data widths of 4 (x4), or 8 (x8), or 16 (x16) bits. Applications can use these memories either as discrete DRAMs or DIMMs. DIMMs are printed circuit board (PCB) modules with several DRAM chips supporting either a 64-bit data width or a 72-bit data width. 72-bit DIMMs are called error-correcting code (ECC) DIMMs since they support 8 bits of ECC in addition to the 64 bits of data.
Servers, cloud, and data center applications typically use x72 ECC DIMMs based on x4 DRAMs, allowing higher density DIMMs and supporting higher RAS (Reliability, Availability, Serviceability) features to minimize the downtime of such applications during memory-related failures. DIMMs based on other x8 and x16 DRAMs are less expensive and are commonly implemented in desktops and notebooks. In addition, applications can use these memories as discrete DRAMs. Hence, flexibility on channel-width is the biggest advantage of standard DDR over the other DDR categories.
Besides performance, DDR5 also introduces several RAS features to ensure channel robustness at increased speeds. Some of these features resulting in higher DDR5 channel robustness include duty cycle adjuster (DCA), on-die ECC, DRAM receive I/O equalization, Cyclic Redundancy Check (CRC) for both RD and WR data, and internal DQS delay monitoring. The following section describes each of these features.
Duty Cycle Adjuster (DCA) for Compensating Duty Cycle Distortion
The duty cycle adjuster allows the host to compensate for duty cycle distortion on all DQS (data strobe)/DQ (data) pins by adjusting the duty cycle inside the DRAM. Hence, the DCA feature enhances the robustness of the read data.
On-die ECC for Enhanced RAS
For every 128 bits of data, DDR5 DRAMs will have 8 bits of storage for ECC. Hence, on-die ECC becomes a powerful RAS feature to protect the memory array against single-bit errors.
DRAM Receive DQ Equalization for Better Margins
Like LPDDR5 DRAMs, DDR5 DRAMs will also support equalization for the WR data. This feature opens the WR DQ eye at the DRAM end, protecting the channel from inter-symbol interference (ISI), improving margins, and enabling higher data rates.
Cyclic Redundancy Check (CRC) for both RD/WR data
While DDR4 supports CRC only for the WR data, DDR5 extends CRC to the RD data, allowing additional protection against errors occurring on the channel.
Internal DQS Delay Monitoring
The internal DQS delay monitoring mechanism allows the host to adjust DRAM delays to compensate for voltage and temperature variations. At DDR5 speeds, the host can use this feature to retrain the channel periodically, compensating for VT variations on delays in the DRAM.