The first step to crafting your DDR solution involves generating the DDR PHY and DDR controller RTL using Synopsys DesignWare DDR PHY Compiler and coreConsultant respectively, as shown in Figure 1. These highly configurable tools and utilities automate the generation of RTL in the context of the SoC.
coreConsultant enables easy configuration of the controller IP and guides the user through implementation and verification as needed. Some of the key parameters, including DDR modes, frequency ratio and memory data width, must be consistent between the DDR PHY and DDR controller. The DDR controller is a highly complex RTL computational block, responsible for interfacing to one or many on-chip busses and organizing memory traffic for improved performance and reduced power via the DFI-compliant interface to the DDR PHY. The DDR controller may be hardened with the DDR PHY or left at the top level. To determine which approach to take, consider the DFI timing and width of the data byte lane. If the DFI interface needs pipeline registers, or the width of the data byte lane is large, hardening the DDR PHY and DDR controller can optimize timing and congestion; otherwise you may leave the controller at the top level. In either case, DFI interoperability between the DDR PHY and controller needs to be maintained.
The DDR PHY Compiler uses a web interface that generates the Verilog model for the DDR PHY. It evaluates more than 60 variables and enables the evaluation of unlimited 'what-if' scenarios. The DDR PHY Compiler also produces an instantly viewable image of the DDR PHY layout, placement scripts, pin list, area and power consumption report, and an RTL model of the PHY.