Configuring DDR Subsystems for Your Design
By Marc Greenberg, Product Marketing Director, Synopsys and Asheesh Khare, FAE Manager, Synopsys
DDR interface IP is used extensively in the semiconductor industry, in many different application areas. Every application has different constraints on the DDR interface. Even within the same application space, design teams creating SoCs that use the same CPUs and have similar functions often use the DDR interface differently.
DDR IP has evolved to be adaptable or configurable to different applications’ constraints. For example, designers using DDR IP like Synopsys’s uMCTL2 memory controller have about 70 compile-time options to decide upon plus 15 further options per port, plus many more run-time options. Combined, most designs need over 100 options to be set correctly for an optimal DDR configuration.
Some key compile-time options that the designer needs to set are: memory type, memory data bus width, memory bus frequency, number of channels, number of AXI ports, width of each port, depth of read and write buffering throughout the design, depth of queues for the CAM-based scheduler, controller: PHY frequency ratio, ECC support, and Quality-of-Service (QoS) options. Additionally, there are many more run-time options especially around the QoS interface and critically in the logical to physical address mapping.