As digital demands continue to accelerate, the transition to 224GEthernet becomes critical. This paper explores how a silicon proven 224G Ethernet PHY IP can propel the future of high-performance computing. 224G Ethernet PHY IP, possibly the most intricate mixed-signal IP to date, offers a balanced solution for tackling increasing bandwidth, lower latency, higher density, and reduced power consumption. This article delves into the meticulous design techniques, innovative architectures, and advanced digital signal processing to deliver high performance, power efficiency, and backward compatibility needed for the reality of 224G SerDes.

The demand for high-speed data transfer is soaring and the need for Terabit Ethernet is real. The Internet Data Center (IDC) predicts that the collective sum of the world’s data will to 175 ZB by 2025. That is a trillion Gigabytes multiplied by 175! This emerging need can be attributed to the growing necessity for higher bandwidth, lower latency, higher density, and lower power - all of which are crucial attributes of today's sophisticated technological infrastructure. This unyielding desire for superior bandwidth and performance is driving the need for 224G.

“If one were able to store 175ZB onto BluRay discs, then you’d have a stack of discs that can get you to the moon 23 times.”  - David Reinsel, Senior VP at IDC

The Imperative of 224GbE

At its core, the essence of SerDes technology lies in its ability to transmit and receive data over a serial link - a task that becomes more challenging as the need for bandwidth increases. It's a constant battle between the growing complexity of systems and the limited amount of power and space that can be worked with. In this regard, 224G Ethernet emerges as the answer for the market, providing the fastest speeds to satisfy the quench for bandwidth. 

Despite multiple challenges, such as increasing design complexity, power constraints, and the need for intricate modulation schemes, the importance of delivering a 224G solution cannot be overstated. Figure 1 shows how IP Nest anticipates three to five 224G designs will start to kick-off in 2023, with the first deployments expected to emerge around 2026. While we talk about the need for 224G Ethernet, it's equally important to identify its early adopters. The initial adoption and application of 224G will be in retimers and gearboxes, switches, AI scaling, optical modules, IO triplets and Field-Programmable Gate Arrays (FPGAs).

Figure 1: IP Nest Predictions for SerDes IP Licenses from 2020 to 2026 showing an increasing trend in 224G Ethernet PHY IP

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224GbE Requires Higher Performance and Lower per Bit Power

The journey to 224G is not without its set of challenges and requirements. In particular, the new standard calls for superior performance and lower per bit power. This necessity arises primarily as the transition from 112G to 224G leads to a doubling of the Nyquist frequency to 56 Gigahertz.

Figure 2: Fragmented market with power vs. Performance tradeoffs

As illustrated in Figure 2, the tradeoff between power and performance in this domain presents a fragmented market landscape. 112G Ethernet established multiple channels and reach types, a trend we anticipate will continue into the 224G realm. Currently, the emphasis on 224G development is primarily targeted towards the Attachment Unit Interface (AUI) and chip-to-module channels. Comparing the signal losses between the 112G and 224G SerDes reveals interesting insights. With the Nyquist frequency doubling, the 224G faces the challenge of delivering considerably higher performance for a given channel or reach type. The introduction of 224G not only signifies a leap in data transmission rates but also calls for substantial advancements in overcoming signal loss and reducing power consumption.

Doubling Speed Comes with a Logarithmic Increase in Complexity


Figure 3: The transition from NRZ to PAM-4

The quest for doubling the Nyquist speed, as we transition from 112G to 224G, introduces a logarithmic increase in complexity. This fact becomes more apparent as we look back. For instance, for Non-Return to Zero (NRZ) analog-type SerDes, the maximum speed established for Ethernet was roughly 28G or 14G Nyquist. This status quo was retained even as we transitioned from NRZ to Pulse Amplitude Modulation 4-level (PAM4) with 56 PHYs. However, with subsequent shifts towards 112G and now 224G, the Nyquist speed has quadrupled to a significant 56 Gigahertz.

Semiconductor physics are not keeping pace with the race against escalating serial link throughput demands

Such heightened speeds pose considerable challenges. There's a marked disproportion in the advancements in 3nm and 5nm fabrication technologies and the increasing bandwidth requirements. Package connector and channel technologies have not seen much progress either. With growing Nyquist frequencies, link losses climb, and without a reduction in the physical distance to faceplate pluggables, reflections are twice as far from the cursor. Insufficient advancements in isolation techniques have also led to increased crosstalk. Thus, the leap from 112G to 224G SerDes doesn't merely double complexity; it catapults it, with the effort to achieve similar performance levels at 224G requiring approximately five times more complexity than the previous generation.

A reality: Exploring the Synopsys 224G Ethernet PHY IP

Figure 4: A high-level diagram of the architecture of 224G SerDes showcases the minimized AFE circuitry needed to reduce parasitics and maximize BW

Navigating the high-speed terrain of 224G involves a finely-tuned architectural approach. This architecture hinges on three pivotal components that together strike a balance between performance, power efficiency, and area optimization. 

  1. Minimized Analog Front End: The first component revolves around minimizing the analog front end to mitigate parasitics and enable a high bandwidth front end. By employing fewer, more efficient transistors, we focus on extracting maximum functionality with minimal components.
  2. Massive Parallelism: The second facet is the introduction of massive parallelism across the system, a necessary attribute to efficiently process high-speed data. This parallelism extends across the ranks and banks of the Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) and permeates the entire clocking structure that operates at lower speeds but with multiple phases.
  3. Digital Domain Parallelism: Finally, this approach is also replicated in the digital domain. Parallelism is integrated within the Maximum Likelihood Sequence Detection (MLSD), Feed Forward Equalization (FFE), and Decision Feedback Equalization (DFE) systems, which also operate at reduced speeds.

Rigorous Design Sensitivity Analysis

Efficiently designing a 224G PHY necessitates rigorous sensitivity analysis for every circuit impairment. It's a delicate balancing act: ensuring each circuit impairment adheres to performance targets without leading to an overdesign that burdens power, area, latency, and cost. This approach involves setting limits that ensure maximum value without excessive design. For instance, if we can achieve the necessary performance with a 7-bit ADC, there is no need to overdesign with an 8 or 9-bit ADC at the expense of power and area. This meticulous process incorporates an extensive list of over 50 impairments, with the principal goal of not only meeting performance targets but also optimizing for power, area, and latency.

Validation Against Massive Channel Library

Figure 5: Channel Magnitude Response vs. Frequency

The design of Synopsys 224G Ethernet PHY IP undergoes rigorous validation against an expansive library of over 50 channels, a diverse collection accumulated from various customers and ecosystem partners. These channels span a wide range, with losses anywhere between 8dB to 45dB. By overlapping the magnitude responses of these channels, we can effectively optimize the design and strike the perfect balance between the analog and Digital Signal Processing (DSP) parts of the system. This method allows to let the analog component carry out the heavy lifting, and then utilize digital assist technologies for further refinement. An additional layer of Forward Error Correction (FEC) is integrated to ensure a near-zero bit error rate (BER). This robust process, coupled with an understanding of the nature of the errors (whether they're deterministic, random, or burst), enables the deployment an FEC technology capable of effectively correcting those errors.

Harnessing Advanced DSP Implementations

Figure 6: Advanced DSP Implementations

Our 224G Ethernet PHY IP implements several digital assist technologies, prominently featuring Maximum Likelihood Sequence Detection (MLSD) for its excellent noise immunity. MLSD harnesses the inherent correlation in the received data stream, employing sequence detection to enhance noise immunity. This correlation can emanate from encoding and decoding processes in the transmitter and receiver, or it could be sourced from channel bandwidth. What correlation essentially does is generate permutations of MLSD response levels in the output. If there's an error in the sequence, MLSD identifies the most probable transmitted sequence by searching for the likeliest received sequence out of all valid permutations created by the MLSD data holding.

Silicon-Proven with Wide Ecosystem Interoperability

Figure 7: Synopsys 224G Ethernet PHY IP displaying TX PAM-4 eyes at 224Gbps

Synopsys made a groundbreaking leap in September 2022, becoming the first company to showcase a 224G SerDes demonstration with an ecosystem partner at ECOC 2022 in Basel, Switzerland. This marked the genesis of a truly tangible 224G Ethernet PHY IP. Since that landmark demo, we've made considerable strides, presenting a range of additional demonstrations highlighting both the transmit and receive performances of the full loopback, at prestigious platforms such as DesignCon and Optical Fiber Communication Conference (OFC) held recently in San Diego, including the OIF interoperability demonstrations, and the TSMC Symposium in Santa Clara.

Arriving at 1.6T with Silicon Proven Synopsys 224G Ethernet PHY IP

Without a doubt, 224G is tough nut to crack. The design margins are extraordinarily tight, making the optimization of individual analog blocks mission-critical, all while maintaining a keen focus on reducing impairments. The task necessitates designing for performance while keeping latency, power, and area in check. Overdesign is not an option. A novel yet straightforward analog architecture is indispensable to maximize bandwidth and reduce parasitics. This means employing fewer transistors that can do the real work efficiently and effectively, which includes elements such as the AFE, PLL, ESD, T-Coils, PMIX, and ADC/DACs. Implementing a high degree of parallelism in the design is a must, but everything needs to be recalibrated and reskewed accurately. This requirement means meticulous design attention is crucial at all levels, including architecture, circuit, and layout.

As we embark on this exciting new era of data transfer rates, it's clear that 224G is no longer a distant vision but a tangible reality. Cracking this tough nut requires a blend of meticulous design, innovative architecture, and strategic optimization. Our silicon-proven 224G Ethernet PHY IP is poised to continue driving the future of high-speed data transfer and keep pushing the boundaries of what's possible. The road to 1.6T is clear.

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