DesignCon 2019

January 29 - 31, 2019

Santa Clara Convention Center

Santa Clara, CA

Network with Synopsys experts and get ready for 32 GT/s PCI Express 5.0 design, overcome DDR5 simulation challenges, and deploy machine learning/AI for hardware design. 

Demo

Anritsu booth # 615, PCI Express 4.0 receiver compliance test using Synopsys DesignWare IP

January 30 & 31 I 12:30 pm - 6:00pm; Exhibit Hall

Demo

Keysight booth # 725, Synopsys DesignWare PHY IP for PCIe Express 5.0 at 32 GT/s

January 30 & 31 I 12:30 pm - 6:00pm; Exhibit Hall