The power profile and switching activity after synthesis will be considerably different from that of the RTL, especially due to datapath gating and clock gating, which significantly reduce the dynamic power of the design. In addition, retiming during synthesis can also change the power profile, since retiming involves moving the pipeline registers into the datapath which could increase the number of sequential cells in the design.
Other factors contribute to the power profile difference as well. The RTL SAIF provided to DC Ultra only has the input ports and the registers annotated. The intermediate logic switching activity is nonexistent as the gates are not yet present. The switching activities of the downstream registers are based purely on the input vectors and the logic function preceding the registers.
For instance, consider the scenario in Figure 4 where the multiplier and adder are surrounded by 3 registers, RegA, RegB, and RegC. In the RTL SAIF, apart from the block’s I/O activities, only the activities at RegA, RegB, and RegC are annotated. The activity of the net connected to the data input of RegB is purely determined by the activity of the net connected to the output pin of RegA and the multiplier logic function. It does not depend on the type of multiplier implemented since there is no gate level information yet. Similarly, the activity of the net connected to the data input of RegC is determined purely by the activity of the net connected to the output pin of RegB and the adder logic function. It does not depend on the type of adder implemented.