Using L1 Sub-States to Reduce Power Consumption in PCI Express-Based Devices
By Scott Knowlton, Sr. Product Marketing Manager, Synopsys, Inc.
In many of today’s mobile multimedia, laptop, computer, server, networking and storage applications, PCI Express® (PCIe) has evolved into the interconnect of choice. PCI Special Interest Group (PCI-SIG), the standards body for PCIe, accomplished this by continually evolving the specification at an incredible rate to improve performance, increase efficiency, and lower power consumption, thereby satisfying the divergent needs of these applications.
Over the last couple of years, PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management. The Latency Tolerance Reporting (LTR) mechanism has been added to the specification, which tells the host the latency tolerance a device has in response to an interrupt from the device. This allows the host to judiciously decide how long to wait before servicing the interrupt from the device in order to coordinate multiple devices and achieve the maximum power optimizations for the system. Another addition, Optimized Buffer Flush/Fill (OBFF), enables the host to provide system state information, via messages, to devices. Devices use this system state information to optimize system power consumption—allowing the Host CPU and memory sub-system to power down and stay in their low power states longer.
The latest ECN from PCI-SIG aims to reduce power consumption while a device is in the suspend state (also known as “standby”) in order to extend the battery life as well as meeting the energy consumption standards set out by governments worldwide. Pulling your tablet or laptop out of your bag during a long flight, only to find that it consumed all of the battery power while it was in standby mode, is one of a business traveler’s nightmares. This experience is a lesson in how non-optimized systems consume a surprising amount of power while in the standby state. PCI-SIG is addressing this situation, as well as meeting the requirements set forth by international regulatory agencies for green, zero-consumption idle power.
While the PCIe specification includes an L1 low-power state, it alone does not meet the thin and light form factor requirements for idle power. Consumers are demanding that these devices have 8 to 10 hours of use time and seemingly an infinite amount of standby time. Of course, this has to be done with minimum added costs during product development while maintaining backwards compatibility.
A PCIe link is a serial link that directly connects two components, such as a Host and a Device as shown in Figure 1. Ignoring the state of the Host or the Device for this discussion, the PCIe link is defined to save power when the controlling link state machine (LTSSM) is in the L1 state. However, the PCIe interface has both analog and digital circuits and the L1 state doesn’t turn off all the analog circuits in the PHY. The Receiver Electrical Idle detector and the transmit common-mode voltage driver continue drawing power. The result is that each lane of the link can consume 10 to 25mW per lane while in standby…quietly draining the device’s battery.