SLM Clock & Delay Monitor IP


Measure Delay Between Edges of a Signal

A clock & delay monitor is a very small piece of IP which can be inserted into silicon without much area overhead.  It doesn’t need an accurate high speed reference clock and provides an accurate time delay measurement. It can be used for measuring clock duty cycle, memory access time, delay line characteristics, etc. It has an IEEE 1500/1687 interface for connecting to test fabric.

Figure 1: Block diagram of Synopsys SLM Clock & Delay Monitor (CDM) IP

Figure 2: Operation concept for duty cycle measurement

Key Features

  • No high-speed high accuracy reference clock required
  • Small footprint
  • Available as soft IP with flexibility to customize
  • EDA software automation

Key Benefits

  • Clock duty cycle quality check
  • Memory access time tracking with BIST
  • Digital delay line test characterization
  • Optimize silicon performance for safety critical applications