By: Rita Horner, Senior Technical Marketing Manager, Synopsys
Designers face new challenges as they address the demand for higher bandwidth combined with faster time-to-market. While higher data rates enable higher bandwidth, they limit transmission distances (due to an increase in channel loss), degrade signal integrity and lower manufacturing yield. Addressing these challenges requires time and resources that can negatively influence system design schedules, or worse, may not be evident while the system is being designed.
PCI-SIG is addressing this challenge with the introduction of the PCI Express 4.0 (PCIe 4.0) lane margining at the receiver feature, allowing system designers to assess the performance variation tolerance of their system. Lane margining allows system designers to use PCIe 4.0 devices to measure the available electrical margin in each system. This article describes the lane margining feature and how it enables designers to deliver a more robust system on time.
Performance Variations within a System
PCI Express, a point-to-point interconnect, supports both internal and external connectivity either across a cable assembly or at the board level. Three common board level interconnect cases are chip-to-chip (with no connectors), an expansion card interface with a board and a connector and a backplane with multiple boards and connectors. In a complex backplane, there are many reasons that the signal integrity may degrade, including cross-talk, reflection, discontinuities, and channel loss. Figure 1 shows an example of channel loss differences across a FR-4 printed circuit board (PCB), where a 24-inch trace has much higher loss at 16 GT/s PCIe 4.0 than at 8 GT/s PCIe 3.0.