The HS Family is supported with a complete suite of development tools.
The ARChitect tool, delivered with every ARC processor, enables rapid processor configuration with an intuitive and easy-to-use GUI. Even though the ARC processors feature a large number of configurable options, they can be configured in less than one hour using the ARChitect tool. The output from ARChitect is Verilog RTL source, the makefiles for the nSIM and xCAM simulators, synthesis scripts for the build tools, configured setup files for the MetaWare compiler, and test benches. The ARC tool suite is fully integrated and the output from all of the tools integrates with the other tools, so the configuration of the processor and any custom instruction extensions are recognized and used by all of the tools.
The MetaWare Development Toolkit is a full and integrated software development environment supporting the HS Family and all ARC Processors. MetaWare includes a highly optimized C/C++ compiler, a debugger that can be used to debug real and virtual targets, and an instruction set simulator. The debugger supports debugging of up to 256 processors in a single session. It supports simultaneous debug of the dual-core and quad-core versions of the HS Family. The source, disassembly, registers and variables for each processor can be viewed side by side or one at a time. The MetaWare Development Toolkit is housed in an Eclipse IDE and can be used with the SmaRT and real-time trace (RTT) options that are available for the ARC HS Family.
The RTT option for the HS Family supports multiple CPUs and is compliant with the Nexus 5001 standard. The RTT option is configurable and can use existing system storage memory, probe memory or a combination of both. There are both on-chip and off-chip capture modes. The capture elements have programmable filters and compression modules to reduce output bandwidth.
The xCAM tool supports 100% cycle accurate simulation of the HS family processors. The tool supports the generation of an unlimited number of configurations of an ARC processor and can be used in conjunction with the ARChitect and MetaWare tool. Synopsys also offers the nSIM Pro instruction set simulator that offers cycle close simulation but at very high speeds. The NCAM mode supports processor centric algorithmic development and optimization.