Cloud native EDA tools & pre-optimized hardware platforms
Derya Eker, ARC Processors Engineering Manager, Synopsys
Diego Gonzalez Montes, ARC Processors R&D Engineer, Synopsys
Today’s high-end systems-on-chips (SoCs) need to handle increasingly compute-intensive workloads but must carefully balance power-to-performance tradeoffs. The demand for wide deployment of artificial intelligence (AI) and deep learning is surging. Face recognition is paramount in mobile phones and extending to smart wearables. Identifying objects and surroundings in augmented- and virtual-reality headsets further push the envelope. Self-driving cars apply deep learning to interpret, predict and respond to data coming from surroundings for safer, smarter autonomous driving.
To optimize for both power and performance, hardware becomes more tightly intertwined with software. Designers must make key architectural choices such as hardware/software workload partitioning and IP vendor selection in the early phases of product development. Today’s SoCs represent a multi-million dollar investment, so the accurate estimation of SoC power is critical to whether your chip is a success or a failure.
Orthogonal to the stimuli used, power estimation accuracy is greatly affected by the applied power estimation methodology combined with the abstraction level of the design that is measured:
The more details captured in the actual implementation, the more accurate power estimate becomes. RTL simulation of a small synthetic benchmark may complete in minutes, but for a netlist it can take hours or days. Simulation of a very deep CNN graph with all implementation details included may require weeks. This simulation time challenge increases the risk that IP vendors may skip such detailed power analysis and accurate power estimation. The result is that an actual power consumption may exceed the power budget; a clear product risk manifesting later during SoC power sign-off phase.
To be able to execute billions of cycles of a CNN graph on a full-layout netlist to achieve maximum accuracy in the power measurements, simulation tools are simply not enough. Synopsys’ ZeBu® Empower provides a solution that can help both IP developers and SoC designers to compute power accurately for hundreds of millions of processed cycles in a matter of minutes or hours instead of weeks or months. ZeBu Empower also supports advanced use modes, including power management verification, comprehensive debug and integration with Synopsys’ verification ecosystem, hybrid emulation with virtual prototypes and architectural exploration and optimization. Therefore, access to ZeBu Empower enables both easy exploration of power/performance tradeoffs with application software on various candidate hardware architectures, and efficiently achieving sign-off quality power estimates, helping to tune power consumption of all elements in a system during the different stages of the design cycle. Designers using Synopsys’ DesignWare®ARC® EV7x Vision Processors are adopting the Zebu Empower software-based power estimation and sign-off flow to get the most accurate and realistic power estimates when using the EV7x processor to handle high-performance deep learning applications.