Designing for Success: USB IP for FinFET Processes
By Morten Christiansen, Technical Marketing Manager, USB IP, Synopsys
SoC designers require continuous area reduction as well as improvements in performance and active and idle power. The continuous search for better transistors led to ultra-thin body, double-gate and Omega-gate transistors. FinFET is the latest development in the transition from discrete transistors via ICs, to VLSI, to ASICs, to SoCs, to complex SoCs. FinFETs enable higher performance, lower active and idle power, and smaller area, and are therefore the key to meeting the area and power requirements for process nodes below 28-nm.
For success when porting IP to FinFETs, IP suppliers must have a good understanding of the challenges associated with FinFETs, including the process complexities in modeling, parasitic extraction, power swings, fin width considerations and even lithography and manufacturing.