Understanding Automotive DDR DRAM

By: Marc Greenberg, Product Marketing Director, Synopsys


Most of the processors contained within automobiles are relatively small and with modest memory requirements that can be served by SRAM and non-volatile memory. The type of computing, image processing, and graphics displays that are possible with a more powerful CPU connected to DRAM have largely been restricted to the non-safety-critical infotainment system in the vehicle – until now. Advanced Driver Awareness Systems (ADAS) and self-driving vehicle systems demand powerful processors that require the memory capacity and bandwidth that is only possible with DRAM. Designers need to understand the benefits of using DRAM in safety critical automotive systems, as well as common concerns regarding error rates and meeting stringent automotive standards such as ISO 26262.


DRAM vs SRAM in Automotive

DRAM chips are prevalent as the main memory in many of our computing devices: home and office computers, servers and networking, mobile devices, televisions, and set-top boxes. The largest DRAM manufacturers represent three of the top 10 largest semiconductor manufacturers, selling a combined 14.7 billion DRAM chips worth a total of $45 billion dollars in 20151.

In the broad market, DRAM devices have long surpassed the SRAM devices that preceded them, with about a 100:1 ratio of DRAM to SRAM revenues1. DRAM devices have higher capacity at lower cost per bit than SRAM, but SRAM devices may have higher reliability and SRAM may be more easily integrated on to the same chip as the CPU. Table 1 shows a comparison of their use in automotive systems.

Table 1: DRAM vs SRAM Use in Automotive Applications

Yet with the huge volume of DRAM devices that are sold, only a tiny fraction of them go into vehicles. In Synopsys’s experience, out of more than 1000 design wins for DDR SDRAM interface IP, only about 5% have gone into chips used in automobiles – and many of those automotive designs that are using DRAM have often been in the region of infotainment rather than in safety-related systems.

Why haven’t DRAM devices expanded out of infotainment and into the safety-critical areas of the automobile in the past? In many cases, SRAM has been a better fit for the safety-critical regions of the automobile, for four key reasons:

  1. Type of computing: The computing needs of safety-critical areas of the automobile have been modest: processing sensor data from the engine, brakes, motion sensors, and driver input to control the engine and braking systems. These systems have computing needs that have generally been supported by SRAM and have not needed the bandwidth and density of DRAM.
  2. Lack of camera input and display output: DRAM are often used to satisfy the computing and buffering needs of high-definition audio-visual input/output. Other than infotainment and rear-view cameras, in the past there generally has not been the need for the bandwidth or memory capacity that is offered by DRAM.
  3. Reliability: Some SRAM devices can operate at higher temperatures than DRAM devices. Also, SRAM devices are generally less susceptible to soft errors and Single Event Upsets (SEU) where data is lost due to atomic particle strikes. If the SRAM needs are very modest – less than a few megabits – then the SRAM may be able to be integrated on to the same system-on-chip (SoC) as the CPU, allowing the reliability to be controlled by the SoC manufacturer.
  4. Real-time operating system (RTOS) needs: DRAM devices need to have a periodic interval where they go off-line to do an internal refresh. In some cases, a real-time operating system may not be able to use a memory that is periodically off-line.

However, things are changing for DRAM in the automobile. Displays are beginning to replace analog gauges for driver information on speed and status – a safety-critical application. The industry is showing huge interest in the concept of the self-driving automobile, and while that is clearly a long-term goal, ADAS features such as advanced navigation systems, adaptive cruise control, lane departure warning, collision warning and avoidance capability, etc. are already becoming prominent in today’s vehicles.


Benefits of DRAM in the Automobile

DRAM is an enabling technology for these three automotive advances:

  1. Displays: High definition displays generally require DRAM, and as displays like instrumentation consoles and heads-up displays will relay safety-critical information to the driver, then DRAM is needed in this safety-critical application.
  2. ADAS systems that process camera and high-bandwidth sensor input: The cameras and other sensors that provide the input to the ADAS system generate a large amount of data which also requires further processing to remove noise, adjust for different lighting conditions, and to identify objects and obstacles. This kind of processing requires the bandwidth and capacity of DRAM.
  3. Self-driving vehicles: Self-driving vehicles require processing of a number of high-bandwidth input sources and intense computation, making DRAM a necessity.

With these applications coming on-line, DRAM will be increasingly required for vehicles. DRAM will not replace SRAM, which will continue to be used for braking and engine management, but will provide new capabilities in ADAS and driver information.

A study by the Highway Data Loss Institute showed that, for similar vehicles available with or without the optional ADAS features of Camera-Based Forward Collision Warning and Lane Departure Warning, the ADAS-equipped vehicles had fewer collisions and at least a 20% reduction in insurance losses for bodily injury liability and medical payments compared to the non-ADAS equipped cars.2

A group of 20 auto manufacturers representing 99% of automobiles sold in the US have said that the ADAS feature of Automatic Emergency Braking (AEB) will be standard across all their vehicles by the year20223. If the driver is distracted, unskilled, or otherwise unable to recognize an imminent forward collision, AEB may automatically applies the brakes, preventing or reducing the severity of the collision.

For people considering a vehicle purchase in the 2017 model year, looking only at mid-sized SUVs (the people’s car of the American suburb), there are at least 12 mid-sized SUVs on the market with available camera-based Forward Collision Warning from a wide range of manufacturers, of which at least nine also offer AEB, and at least four manufacturers provide Forward Collision Warning as a standard feature on all the mid-sized SUVs within their range.


Concerns When Adding DRAM to Automotive Systems

The core of a DRAM chip is an analog array of bit-cells that operate by storing a small amount of charge on a capacitor within each bit-cell – just a few tens of femtoFarads or just a few tens of thousands of electrons per bit, on a DRAM device with 4 or 8 billion bits per die. When introducing DRAM into a vehicle, we need to make some adaptations to the system to allow for the expected reliability under the operating conditions typically found in the vehicle.

One of the fundamental issues with DRAM bit-cells is that they leak charge and need to be periodically refreshed to avoid the loss of data in the memory. The rate of leakage is dependent on the temperature, leaking more at higher temperatures. Many automotive manufacturers have opted to put their camera-based ADAS modules on the windshield, where they benefit from being cleaned when the windshield is cleaned, but they also suffer from being in direct sunlight and potentially at a very high temperature when the vehicle has been parked in a hot climate in full sun. The operating temperature range for most automotive applications surpasses the normal DRAM operating range common to PC type applications which results in specially designed DRAMs targeted towards automotive applications.

The most common DRAM device for new ADAS designs is the LPDDR4 SDRAM. LPDDR4, originally designed for mobile devices offers a balance of capacity, speed and form factor that is attractive for automotive applications. As a result, LPDDR4 has been automotive qualified by DRAM manufacturers and is available in automotive temperature grades.

DRAM devices are also susceptible to soft errors due to Single Event Upsets (SEUs) – the effect of ionizing radiation on the DRAM device. In the case of an atomic decay within the DRAM device, or the effect of a neutrino or other cosmic particle strike on an atomic nucleus within the DRAM, a nearby bit-cell may lose its charge and again error correction should be employed to recover the lost data.

Even with careful physical interface design, at LPDDR4 data transmission speeds, there is a non-zero bit error rate, so the risk of data transmission errors must also be addressed.

There are a few possible ways to mitigate possible errors that may occur in DRAM devices to prevent the errors from propagating into the rest of the system. The DRAM manufacturer may attempt to create a bit-cell that is more temperature resistant, or the DRAM manufacturer may introduce error correction within the DRAM die to correct for the bit-cells which have lost their charge between refreshes. Even if error correction is present within the DRAM die, the SoC designer may also introduce error correction on the DRAM interface to correct errors in the DRAM.

In traditional DDR DRAM designs such as servers and networking chips, any error correction is usually transmitted side-band to the DRAM data. However, when using LPDDR4 devices, the arrangement of LPDDR4 into 16-bit channels, 2 channels per die, 2-4 dies per package, 4 channels per package means that it is highly impractical to implement sideband pins with which to transmit sideband Error Correcting Code (ECC) data. In that case, an in-line ECC scheme may be used, which transmits the ECC data on the same data pins as the data it protects (Figure 1).

Figure 1: Comparison of sideband vs in-line ECC

Meeting Automotive Standards

When considering a SoC design to connect with off-chip DRAM, the SoC may be required to meet certain automotive reliability standards – typically AEC-Q100 and ISO 26262.

Hardened IP for implementing the DRAM interface can meet AEC-Q100 requirements with careful design and characterization. This includes both reliability and temperature components.

ISO 26262 has several requirements with components of process, design and certification among them. A core requirement is to have a defined design safety methodology and a safety manager tasked with implementing the processes. The DRAM interface IP requires extra circuits to periodically test the interface to make sure that the majority of errors that violate safety goals can be detected within a fraction of a second. Typically, a third-party certification is performed to rate the compliance of the design and assign an ASIL rating. The majority of automotive designs require at least ASIL B protection of the DRAM interface, while some designs may require ASIL D, the highest level of protection reserved for safety processors and their associated circuits.



DRAM devices are an enabling technology for advancements in automotive safety, features, and convenience. With careful design and stringent process, DRAM can be introduced into safety-critical areas of the automobile to provide high bandwidth and large capacity to enable the computing necessary for driver information systems, ADAS, and self-driving vehicles.

Synopsys provides a range of DDR interface IP including PHYs, Controllers, Verification IP, architecture design models, and prototyping systems. Ask your Synopsys representative about automotive-qualified IP for your next automotive design.



1IC Insights McClean report, 2016
2Highway Data Loss Institute, 2016
3National Highway Transportation Safety Administration