Synopsys Webinar | Available On-Demand

Complexity brought on by advanced process nodes have opened the door to challenges in achieving optimal power, performance, and area (PPA). Manual methods are no longer viable given shrinking market windows. The need to drive for better results faster is increasing, and traditional methods cannot keep pace often taking months of tuning using 100s of trials. Even then, results are not optimal. AI-driven technology can help.


This Synopsys webinar discusses the challenges facing engineers creating complex designs and introduces Synopsys Design Space Optimization solution,™. The industry’s first autonomous artificial intelligence (AI) application for chip design, Synopsys searches for optimization targets in very large solution spaces of chip design, utilizing reinforcement learning to enhance power, performance, and area. RTL-to-GDSII full flow optimization unlocks PPA potential across both logical and physical domains with reported productivity enhancements of more than 3x, power reductions of up to 15%, and substantial die size reductions. We’ll explore case studies from AMD, Intel, and STMicro on how they are applying this technology to surpass the most challenging goals in chip design and reach new levels of productivity. 


Listed below is the industry leader scheduled to speak.

James Chuang headshot

James Chuang

Product Management Manager

James Chuang is a Product Manager at Synopsys. He has worked in the EDA industry for more than 15 years, with experience in Digital Implementation and Signoff solutions. He is currently responsible for Product Management for Synopsys Fusion Compiler™ and Synopsys™ at Synopsys.

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