2025-12-04 00:51:12
The Synopsys LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps. With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.
LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets. The Synopsys LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including:
- Traditional mobile environments
- Consumer products
- Automotive solutions
- Artificial intelligence
- Data center applications
Synopsys LPDDR6/5X/5 PHY IP
Highlights
Products
Downloads and Documentation
- Support for LPDDR6 with data rates up to 14.4 Gbps, LPDDR5X up to 10.67 Gbps, and LPDDR5 up to 6.4 Gbps
- Flexible implementation to support discrete DRAM-on-PCB systems, Package-On-Package (PoP), or emerging modules such as LPCAMM2 and SOCAMM
- Support for East-West and North-South die edge placement, including options to reduce the die edge “beachfront” required for SoCs with many memory interfaces
- DFI 5.2 compliant controller interface
- PHY independent, firmware-based training using an embedded calibration processor
- Support for up to 4 hardware trained states/frequencies
- I/Os feature transmitter pre-emphasis, time domain DCA, programmable output impedance/slew rate/ODT, and 1 or 2 taps of Decision Feedback Equalization
- Designed for rapid integration with Synopsys LPDDR5X/5/4X controller IP and verification IP for a complete DDR IP solution
| Description: |
LPDDR6/5X/5 PHY - TSMC N2P |
| Name: |
dwc_lpddr6_phy_tsmc2p |
| Version: |
1.10a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes Synopsys PHY IP LPDDR6 Compilation Using the LC and FC End-User Platform Application Note (Version 2023.08) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 ATE Firmware Application Note (FW Version: A-2025.09) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 CTB and Verification Application Note (FW Version: A-2025.09) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY Backdoor Support Application Note (Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY Initialization (PHYInit) Software Overview Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY Quickboot Application Note (FW Version: A-2025.09) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY Signal Integrity Application Note (Version: 0.70a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY ZEBU Emulation Compilation Application Note (Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY coreKit User Guide (Doc Version: 1.01a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 Training Firmware Application Note (FW Version: A-2025.09) ( PDF | HTML )
Databooks Synopsys PHY IP LPDDR6/5X/5 PHY Databook for TSMC N2P (PHY Version: 1.10a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY Utility Block Databook (PUB Version: 1.01a_d1) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR6/5X/5 PHY Implementation Guide (Doc. Version 1.30a) ( PDF | HTML )
Release Notes Synopsys PHY IP LPDDR6/5X/5 PHY Release Notes for TSMC N2P (PHY Version: 1.10a) ( TEXT )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dwc_lpddr6_phy_tsmc2p12 |
| Product Code: |
J060-0 |
| Description: |
LPDDR6/5X/5 PHY - TSMC N3P |
| Name: |
dwc_lpddr6_phy_tsmc3pff12 |
| Version: |
1.10a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDRPHY Backdoor Support Application Note (Version: 1.10a) ( PDF | HTML )
Synopsys PHY IP LPDDR6 Compilation Using the LC and FC End-User Platform Application Note (Version 2023.08) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 ATE Firmware Application Note (FW Version: A-2025.06) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 Background Restore Firmware (Doc. Version 0.14a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 CTB and Verification Application Note (FW Version: A-2025.06) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY Initialization (PHYInit) Software Overview Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY Quickboot Application Note (FW Version: A-2025.06) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY Signal Integrity Application Note (Version: 0.70a_cust) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY coreKit User Guide (Doc Version: 1.20a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 Training Firmware Application Note (FW Version: A-2025.06) ( PDF | HTML )
Databooks Synopsys PHY IP LPDDR6/5X/5 PHY Databook for TSMC N3P (PHY Version: 1.10a) ( PDF | HTML )
Synopsys PHY IP LPDDR6/5X/5 PHY Utility Block Databook (PUB Version: 1.20a_d1) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR6/5X/5 PHY Implementation Guide (Doc. Version 1.20a) ( PDF | HTML )
Release Notes Synopsys PHY IP LPDDR6/5X/5 PHY Release Notes for TSMC N3P (PHY Version: 1.10a) ( TEXT )
|
| Download: |
dwc_lpddr6_phy_tsmc3pff12 |
| Product Code: |
J224-0 |
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