- Silicon Design & Verification
- Products
- Solutions
- Resources
- Services
- Community
- Training
- Silicon IP
- Products
- Markets
- Newsletter
- Customer Success
- News
- Resources
- Software Integrity
- Tools & Services
- Solutions
- Training
- Customers
- Resources
- Partners
- Blog
- Company
- About Us
- Investor Relations
- Community
- Newsroom
- Resources
- Careers
DesignWare Enhanced Universal DDR Protocol Controller (uPCTL2)
The DesignWare® Enhanced Universal Protocol Controller (uPCTL2) is fully configurable protocol controller that allows designers to generate a DDR interface that is optimized for latency, bandwidth, and area. The configurable uPCTL2 allows for the generation of DDR controllers that meet or exceed the requirements of designs ranging from high-performance networking to low-power, cost-sensitive mobile products. uPCTL2 supports the JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs.
The DesignWare ® Enhanced Universal DDR Protocol Controller (uPCTL2) serves the memory control needs of applications where memory scheduling is done on the host side or interconnect by an external scheduler. This advanced protocol controller accepts memory access requests from a single application-side host port using AMBA (AXI4, AXI) bus interfaces or Synopsys’ custom defined host interface H-IF for single-port ultra low latency configurations.
The uPCTL2’s low-power features make it useful in power-sensitive designs, and uPCTL2’s reliability, availability, and serviceability (RAS) features meet the needs of the most demanding enterprise systems.
The uPCTL2 connects to DDR PHYs via a DFI interface to create a complete memory interface and control solution. The controller includes software configuration registers, which are accessed through an AMBA APB interface.
DesignWare DDR Complete Solution Datasheet DesignWare Enhanced Universal DDR Memory and Protocol Controller IP Datasheet
- Join your own scheduler to a single-port enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3 and LPDDR4 SDRAMs
- Compatible with all Synopsys DesignWare DDR PHYs (excluding DDR2/DDR PHYs)
- DFI 4.0, DFI 3.1 or DFI 2.1 compliant interface to DDR PHY (DFI 3.1 is backward compatible with DFI 2.1)
- Boot-time programmable frequency ratio
- Data rates up to 3200 Mbps in 1:2 frequency ratio, using an 800 MHz controller clock and 1600 MHz memory clock (Dependent on process and PHY chosen)
- Data rates up to 1600 Mbps in 1:1 frequency ratio, using an 800 MHz controller clock and 800 MHz memory clock (Dependent on process and PHY chosen)
| Description: | DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2 |
| Name: | dwc_ddr_upctl2 |
| Version: | 3.90a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Databooks DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) Databook ( PDF ) DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) Databook - … ( PDF ) Datasheets DesignWare DDR Complete Solution Datasheet ( PDF ) DesignWare Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF ) Installation Guide DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) Installation Guide ( PDF ) Release Notes DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) Release Notes ( PDF ) Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With … ( PDF ) Starblaze Technology Achieves Volume Production of SSD Controller SoC With … ( PDF ) User Guides DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) User Guide ( PDF ) DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) User Guide - … ( PDF ) White Paper Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures ( PDF ) |
| Toolsets: | Qualified Toolsets |
| Download: | DDR-U-PCTL2 |
| Product Code: | B624-0 |