The DesignWare® Enhanced Universal Protocol Controller (uPCTL2) is fully configurable protocol controller that allows designers to generate a DDR interface that is optimized for latency, bandwidth, and area. The configurable uPCTL2 allows for the generation of DDR controllers that meet or exceed the requirements of designs ranging from high-performance networking to low-power, cost-sensitive mobile products. uPCTL2 supports the JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs.
The DesignWare ® Enhanced Universal DDR Protocol Controller (uPCTL2) serves the memory control needs of applications where memory scheduling is done on the host side or interconnect by an external scheduler. This advanced protocol controller accepts memory access requests from a single application-side host port using AMBA (AXI4, AXI) bus interfaces or Synopsys’ custom defined host interface H-IF for single-port ultra low latency configurations.
The uPCTL2’s low-power features make it useful in power-sensitive designs, and uPCTL2’s reliability, availability, and serviceability (RAS) features meet the needs of the most demanding enterprise systems.
The uPCTL2 connects to DDR PHYs via a DFI interface to create a complete memory interface and control solution. The controller includes software configuration registers, which are accessed through an AMBA APB interface.
DesignWare DDR Complete Solution Datasheet
DesignWare Enhanced Universal DDR Memory and Protocol Controller IP Datasheet
Description: | DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2 |
Name: | dwc_ddr_upctl2 |
Version: | 3.91a |
STARs: | Open and/or Closed STARs |
myDesignWare: | Unsubscribe |
Product Type: | DesignWare Cores |
Documentation: |
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Toolsets: | Qualified Toolsets |
Download: | dw_iip_DWC_ddr_umctl2 |
Product Code: | B624-0 |