2025-10-02 05:05:24
The Synopsys DDR5 MRDIMM2 PHY IP is part of a complete IP solution including PHY and Controller enabling ASIC, Application-specific standard products (ASSP), and System-on-Chip (SoC) applications requiring high-performance DDR5 MRDIMM and RDIMM interfaces operating at up to 12,800 Mbps. By operating at higher data-rates and allowing simultaneous access of up to four cache lines, DDR5 MRDIMMs provide a significantly increased BW and performance, compared to the traditional RDIMMs. The Synopsys DDR5 MRDIMM2 PHY IP is ideal for systems that require high speed, high-performance, and high-capacity memory solutions, typically using registered and multiplexed-rank memory modules (RDIMMs and MRDIMMs) with up to 4 physical ranks.
Synopsys DDR5 MRDIMM PHY IP
Highlights
Products
Downloads and Documentation
- Supports JEDEC standard DDR5 RDIMMs and Gen2 MRDIMMs
- High-performance DDR PHY supporting data rates up to 12.8 Gbps
- Supports 1N and 2N modes for both DDR5 R/MRDIMMs
- PHY independent, firmware-based training using an embedded calibration processor
- High speed IO, 8-tap DFE on IO Receiver, regulated clock path both RD and WR sides
- VT compensated delay lines for DQS centering, read/write 1D and 2D training, and per-bit deskew on both read and write data paths
- PUB / data path to run at DFICLK = 1.6GHz (for 12.8Gbs data-rate) at DFI 1:4 ratio
- DFI 5.2 compliant controller interface
- Designed for rapid integration with Synopsys PHY and controller for a complete DDR IP solution
| Description: |
DDR5 MRDIMM2 PHY - TSMC N3P |
| Name: |
dwc_ddr5_mrdimm2_phy_tsmc3pff12 |
| Version: |
2.00a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDRPHY Backdoor Support Application Note (Version: 1.10a) ( PDF | HTML )
Synopsys PHY IP DDR5 MRDIMM2 Compilation Using the LC and FC End-User Platform Application Note (Version 2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 MRDIMM2 PHY ATE Firmware Application Note (FW Version: A-2025.08) ( PDF | HTML )
Synopsys PHY IP DDR5 MRDIMM2 PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys PHY IP DDR5 MRDIMM2 PHY CTB and Verification Application Note (FW Version: A-2025.08) ( PDF | HTML )
Synopsys PHY IP DDR5 MRDIMM2 PHY Initialization (PHYInit) Software Overview Application Note (Version 1.00a) ( PDF | HTML )
Synopsys PHY IP DDR5 MRDIMM2 PHY Interconnect Signal and Power Integrity Guidelines Application Note (Version 0.10a) ( PDF | HTML )
Synopsys PHY IP DDR5 MRDIMM2 PHY Training Firmware Application Note (FW Version: A-2025.08) ( PDF | HTML )
Synopsys PHY IP DDR5 MRDIMM2 PHY coreKit User Guide Application Note (Version: 1.40a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5 MRDIMM2 PHY Databook for TSMC3PFF12 (PHY Version: 2.00a) ( PDF | HTML )
Synopsys PHY IP DDR5 MRDIMM2 PHY Utility Block (PUB) Databook (PUB Version: 1.40a) ( PDF | HTML )
Implementation Guide Synopsys PHY IP DDR5 MRDIMM2 PHY Implementation Guide (Version 1.20a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR5 MRDIMM2 PHY Databook for TSMC3PFF12 Release Notes (PHY Version: 2.00a) ( TEXT )
|
| Download: |
dwc_ddr5_mrdimm2_phy_tsmc3pff12 |
| Product Code: |
J280-0 |