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The Synopsys DDR5 MRDIMM2 PHY IP is part of a complete IP solution including PHY and Controller enabling ASIC, Application-specific standard products (ASSP), and System-on-Chip (SoC) applications requiring high-performance DDR5 MRDIMM and RDIMM interfaces operating at up to 12,800 Mbps. By operating at higher data-rates and allowing simultaneous access of up to four cache lines, DDR5 MRDIMMs provide a significantly increased BW and performance, compared to the traditional RDIMMs. The Synopsys DDR5 MRDIMM2 PHY IP is ideal for systems that require high speed, high-performance, and high-capacity memory solutions, typically using registered and multiplexed-rank memory modules (RDIMMs and MRDIMMs) with up to 4 physical ranks.
Highlights & Key Features
- Supports JEDEC standard DDR5 RDIMMs and Gen2 MRDIMMs
- High-performance DDR PHY supporting data rates up to 12.8 Gbps
- Supports 1N and 2N modes for both DDR5 R/MRDIMMs
- PHY independent, firmware-based training using an embedded calibration processor
- High speed IO, 8-tap DFE on IO Receiver, regulated clock path both RD and WR sides
- VT compensated delay lines for DQS centering, read/write 1D and 2D training, and per-bit deskew on both read and write data paths
- PUB / data path to run at DFICLK = 1.6GHz (for 12.8Gbs data-rate) at DFI 1:4 ratio
- DFI 5.2 compliant controller interface
- Designed for rapid integration with Synopsys PHY and controller for a complete DDR IP solution
Product Details
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