Description: |
USB 3.0 femtoPHY - GF 12LP x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_gf12lp_x1ns |
Version: |
4.04a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databook DesignWare Cores SuperSpeed USB 3.0 femtoPHY for GF 12-nm x1 LP 0.8/1.8 V Databook (PHY Version: 4.04a) ( HTML | PDF )
Release Notes DesignWare Cores SuperSpeed USB 3.0 femtoPHY for GF 12-nm x1 LP 0.8/1.8 V (PHY Version: 4.04a) ( TXT )
|
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dwc_usb3_femtophy_otg_gf12lp_x1ns |
Product Code: |
D873-0 |
| |
Description: |
USB 3.0 femtoPHY - GF 12LP+ x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_gf12lpp_x1ns |
Version: |
4.00a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databook DesignWare Cores SuperSpeed USB3.0 femtoPHY for GF 12-nm x1 LPP 0.8/1.8 V Databook (PHY Version: 4.00a) ( HTML | PDF )
Release Notes DesignWare Cores SuperSpeed USB3.0 femtoPHY for GF 12-nm x1 LPP 0.8/1.8 V Release Notes (PHY Version: 4.00a) ( TXT )
|
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dwc_usb3_femtophy_otg_gf12lpp_x1ns |
Product Code: |
F048-0 |
| |
Description: |
USB 3.0 femtoPHY - GF 28SLP x1 OTG, East/West Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_gf28slp_x1ew |
Version: |
4.00a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databooks DesignWare Cores SuperSpeed USB 3.0 femtoPHY for GLOBALFOUNDRIES 28-nm SLP 1.0/1.8 V Databook ( PDF )
DesignWare Cores SuperSpeed USB 3.0 femtoPHY for GLOBALFOUNDRIES 28-nm SLP 1.0/1.8 V Databook (PHY Version: 4.00a) ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
USB3-femtoPHY_GF_28SLP_A |
Product Code: |
C190-0 |
| |
Description: |
USB 3.0 femtoPHY - SMIC 28HKMG x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_smic28hkmg_x1ns |
Version: |
4.01a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Changes (PHY Version: 4.01a) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 femtoPHY for SMIC 28-nm HKMG 0.9/1.8 V Databook (PHY Version: 4.01a) ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
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USB3-femtoPHY_SMIC_28HK18 |
Product Code: |
B584-0 |
| |
Description: |
USB 3.0 femtoPHY - SS 10LPE x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_ss10lpe_x1ns |
Version: |
4.06a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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USB3-femtoPHY_SS_10LPE |
Product Code: |
E146-0 |
| |
Description: |
USB 3.0 femtoPHY - SS 11LPP x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_ss11lpp_x1ns |
Version: |
4.00b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databook DesignWare® Cores SuperSpeed USB 3.0 femtoPHY for Samsung 11-nm LPP 0.8/1.8 V Databook (PHY Version: 4.00b) ( HTML | PDF )
Release Notes DesignWare® Cores SuperSpeed USB 3.0 femtoPHY for Samsung 11-nm LPP 0.8/1.8 V Release Notes (PHY Version: 4.00b) ( TEXT )
|
Download: |
dwc_usb3_femtophy_otg_ss11lpp_x1ns |
Product Code: |
D832-0 |
| |
Description: |
USB 3.0 femtoPHY - SS 14LPP x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_ss14lpp_x1ns |
Version: |
4.07b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databooks Current Databook With Changes (PHY Version: 4.07a) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 femtoPHY for Samsung 14-nm LPP 0.8/1.8 V Databook (PHY Version: 4.07a) ( HTML | PDF )
Release Notes DesignWare Cores SuperSpeed USB 3.0 femtoPHY for Samsung 14-nm LPP 0.8/1.8 V ( TXT )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
dwc_usb3_femtophy_otg_ss14lpp_x1ns |
Product Code: |
C258-0 |
| |
Description: |
USB 3.0 femtoPHY - SS 14LPU x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_ss14lpu_x1ns |
Version: |
4.00a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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DesignWare Cores |
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dwc_usb3_femtophy_otg_ss14lpu_x1ns |
Product Code: |
G335-0 |
| |
Description: |
USB 3.0 femtoPHY - TSMC 12FFC x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_tsmc12ffc_x1ns |
Version: |
4.04a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databook DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 12-nm FFC 0./1.8 V Databook (PHY Version 4.04a_d1) ( PDF | HTML )
Release Notes DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 12-nm FFC 0./1.8 V (Release Notes:4.04a) ( TXT )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
dwc_usb3_femtophy_otg_tsmc12ffc_x1ns |
Product Code: |
C523-0 |
| |
Description: |
USB 3.0 femtoPHY - TSMC 16FF+GL x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_tsmc16ffpgl_x1ns |
Version: |
4.12a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 16-nm FFPGL 0.8/1.8 V Databook (PHY Version 4.12a) ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 femtoPHY for TSMC 16-nm FFPGL 0.8/1.8 V Databook With Change Bars (PHY Version: 4.12a) ( PDF )
Datasheet Synopsys USB 3.0 femtoPHY IP ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
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USB3-femtoPHY_TSMC_16FFPGL |
Product Code: |
A373-0 |
| |
Description: |
USB 3.0 femtoPHY - TSMC 16FF+LL x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_tsmc16ffpll_x1ns |
Version: |
4.12a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 16-nm FFPLL 0.8/1.8 V Databook (PHY Version 4.12a) ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 femtoPHY for TSMC 16-nm x1 FFPLL 0.8/1.8 V Databook With Change Bars (PHY Version: 4.12a) ( PDF )
Datasheet Synopsys USB 3.0 femtoPHY IP ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
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USB3-femtoPHY_TSMC_16FFPLL |
Product Code: |
A365-0 |
| |
Description: |
USB 3.0 femtoPHY - TSMC 16FFC x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_tsmc16ffc_x1ns |
Version: |
4.03b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 16-nm FFC 0.8/1.8 V Databook ( HTML | PDF )
Release Notes DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 16-nm FFC 0.8/1.8 V ( TXT )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
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USB3-femtoPHY_TSMC_16FFC |
Product Code: |
B868-0 |
| |
Description: |
USB 3.0 femtoPHY - TSMC 22ULP18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_tsmc22ulp18_x1ns |
Version: |
4.02a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databook DesignWare Cores SuperSpeed USB3.0 femtoPHY for TSMC 22nm ULP 0.9/1.8 V (PHY Version: 4.02a) ( PDF | HTML )
Release Notes DesignWare Cores SuperSpeed USB3.0 femtoPHY for UMC 22nm x1 ULP 0.9/1.8 V Release Notes (PHY Version: 4.02a) ( TXT )
|
Download: |
dwc_usb3_femtophy_otg_tsmc22ulp18_x1ns |
Product Code: |
E129-0 |
| |
Description: |
USB 3.0 femtoPHY - TSMC 28HPC+ x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_tsmc28hpcp18_x1ns |
Version: |
4.05a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 28-nm HPCP 0.9/1.8 V Databook (PHY Version: 4.05a) ( PDF | HTML )
Release Notes DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 28-nm x1 HPCP 0.9/1.8 V Release Notes (PHY Version: 4.05a) ( TXT )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
dwc_usb3_femtophy_otg_tsmc28hpcp18_x1ns |
Product Code: |
B673-0 |
| |
Description: |
USB 3.0 femtoPHY - UMC 22ULP18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_umc22ulp18_x1ns |
Version: |
4.02a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databook DesignWare Cores SuperSpeed USB3.0 femtoPHY for UMC 22nm x1 ULP 0.9/1.8 V Databook (PHY Version: 4.02a) ( PDF | HTML )
Release Notes DesignWare Cores SuperSpeed USB3.0 femtoPHY for UMC 22nm x1 ULP 0.9/1.8 V Release Notes (PHY Version 4.02a) ( TXT )
|
Download: |
dwc_usb3_femtophy_otg_umc22ulp18_x1ns |
Product Code: |
E884-0 |
| |
Description: |
USB 3.0 femtoPHY - UMC 28HLP18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_umc28hlp18_x1ns |
Version: |
4.01a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databooks DesignWare Cores USB 3.0 femtoPHY for UMC 28-nm HLP 1.05/1.8 V Databook (PHY Version: 4.01a) ( PDF )
DesignWare® Cores USB 3.0 femtoPHY for UMC 28-nm HLP 1.05/1.8 V Databook With Change Bars (PHY Version: 4.01a) ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
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USB3-femtoPHY_UMC_28HLP18 |
Product Code: |
A358-0 |
| |
Description: |
USB 3.0 femtoPHY - UMC 28HPC18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_umc28hpc18_x1ns |
Version: |
4.00a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databooks DesignWare Cores USB 3.0 femtoPHY for UMC 28-nm HPC 0.9/1.8 V Databook (PHY Version: 4.00a) ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 femtoPHY for UMC 28-nm x1 HPC 0.9/1.8 V Databook With Change Bars (PHY Version: 4.00a) ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
USB3-femtoPHY_UMC_28HPC18 |
Product Code: |
A355-0 |
| |
Description: |
USB 3.0 femtoPHY-TSMC 28HPC18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_tsmc28hpc_x1ns |
Version: |
4.04a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 28-nm HPC 0.9/1.8 V Databook (PHY Version: 4.04a) ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 femtoPHY for TSMC 28-nm x1 HPC 0.9/1.8 V Databook With Changes (PHY Version: 4.04a) ( PDF )
Datasheet Synopsys USB 3.0 femtoPHY IP ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-femtoPHY_TSMC_28HPC18 |
Product Code: |
A705-0 |
| |
Description: |
USB 3.0 femtoPHY-TSMC 28HPM18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3_femtophy_otg_tsmc28hpm_x1ns |
Version: |
4.03a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks DesignWare Cores SuperSpeed USB 3.0 femtoPHY for TSMC 28-nm HPM 0.9/1.8 V Databook (PHY Version: 4.03a) ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 femtoPHY for TSMC 28-nm x1 HPM 0.9/1.8 VDatabook With Changes (PHY Version: 4.03a) ( PDF )
Datasheet Synopsys USB 3.0 femtoPHY IP ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
USB3-femtoPHY_TSMC_28HPM18 |
Product Code: |
A624-0 |
| |
Description: |
USB 3.0 PHY - FUJ 40LP25 x1 OTG |
Name: |
dwc_usb3phy_otg_fuj40lp_x1 |
Version: |
2.00b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Product Type: |
DesignWare Cores |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare® Cores SuperSpeed USB 3.0 PHY for Fujitsu 40-nm LP 1.1/2.5 V Databook ( PDF )
|
Download: |
USB3-PHY_FUJ_40LP25 |
| |
Description: |
USB 3.0 PHY - GF 28SLP18 x1 OTG, East/West poly orientation |
Name: |
dwc_usb3phy_otg_gf28slp_x1ew |
Version: |
2.6a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Product Type: |
DesignWare Cores |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 PHY for GLOBALFOUNDRIES 28-nm SLP 1.0/1.8 V ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_GF_28SLP18_x1EW |
Product Code: |
4762-0 |
| |
Description: |
USB 3.0 PHY - GF 40LP25 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_gf40lp_x1ns |
Version: |
2.3b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 PHY for GLOBALFOUNDRIES 40-nm LP 1.1/2.5 V Databook ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_GF_40LP25 |
Product Code: |
7334-0 |
| |
Description: |
USB 3.0 PHY - GF 55LPE25 x1 |
Name: |
dwc_usb3phy_otg-gf55lpe-x1 |
Version: |
1.0b |
ECCN: |
5E991/NLR |
STARs: |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 PHY for GLOBALFOUNDRIES 55-nm LPE 1.2/2.5 V Databook ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_GF_55LPE |
Product Code: |
6545-0 |
| |
Description: |
USB 3.0 PHY - GF 65G x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_gf65g_x1ns |
Version: |
1.0b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 PHY for GLOBALFOUNDRIES 65-nm G 1.0/2.5 V Databook ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_GF_65G_A |
Product Code: |
A341-0 |
| |
Description: |
USB 3.0 PHY - GF 65LPE25 x1 |
Name: |
dwc_usb3phy_otg-gf65lpe-x1 |
Version: |
1.2a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Change Bars (PHY Version 1.20a) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for GLOBALFOUNDRIES 65-nm LPE 1.2/2.5 V Databook (PHY Version: 1.20a) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_GF_65LPE |
Product Code: |
6520-0 |
| |
Description: |
USB 3.0 PHY - Samsung 28LPP18 x1, OTG, North/South (vertical) poly orientation |
Name: |
dwc_usb3phy_otg_samsung28lpp_x1ns |
Version: |
2.4a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Change Bars (PHY Version 2.40a) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for Samsung 28-nm LPP 1.0/1.8 V Databook (PHY Version: 2.40a) ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
USB3-PHY_SS_28LPP |
Product Code: |
A718-0 |
| |
Description: |
USB 3.0 PHY - SMIC 110G x1 |
Name: |
dwc_usb3phy_otg_smic110g_x1 |
Version: |
1.1c |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Databook DesignWare Cores SuperSpeed USB 3.0 PHY for SMIC 110-nm G 1.2/3.3 V Databook (PHY Version: 1.10c) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_SMIC_110G |
Product Code: |
7338-0 |
| |
Description: |
USB 3.0 PHY - SMIC 28PS18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_smic28ps_x1ns |
Version: |
4.03a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores USB 3.0 femtoPHY for smic28ps 105/18V Databook (PHY Version: 4.03a) ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
USB3-femtoPHY_SMIC_28PS18 |
Product Code: |
A955-0 |
| |
Description: |
USB 3.0 PHY - SMIC 65LL25 x1 |
Name: |
dwc_usb3phy_otg-smic65ll-x1 |
Version: |
1.2d |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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DesignWare Cores |
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Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Changes (PHY Version: 1.20d) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for SMIC 65-nm LL 1.2/2.5 V Databook (PHY Version: 1.20d) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
DisplayLink Achieves First-Pass Silicon Success with Synopsys USB 3.0 IP ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
Fujitsu Semiconductor Selects Synopsys DigRFv4 M-PHY and DigRF 3G PHY IP for Customer's 2G/3G/4G Baseband Design ( PDF )
Realtek Achieves First Silicon Success for Industry's First Certified USB 3.0 Card Reader with Synopsys USB 3.0 IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_SMIC_65LL25 |
Product Code: |
4790-0 |
| |
Description: |
USB 3.0 PHY - SS 14LPP x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_ss14lpp_x1ns |
Version: |
3.04a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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USB3-PHY_SS_SAMS_14LPP_A |
Product Code: |
C212-0 |
| |
Description: |
USB 3.0 PHY - TSMC 28HP18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg-tsmc28hp-x1ns |
Version: |
2.3b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Change Bars (PHY Version: 2.30b) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 28-nm HP 0.85/1.8 V Databook (PHY Version: 2.30b) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_28HP18_x1 |
Product Code: |
8786-0 |
| |
Description: |
USB 3.0 PHY - TSMC 28HPC+25 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_tsmc28hpcp25_x1ns |
Version: |
3.01a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Change Bars (PHY Version: 3.01a) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 28-nm HPCP 0.9/2.5 V Databook (PHY Version: 3.01a) ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
USB3-PHY_TSMC_28HPCP25 |
Product Code: |
B791-0 |
| |
Description: |
USB 3.0 PHY - TSMC 28HPC18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_tsmc28hpc18_x1ns |
Version: |
2.6b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Product Type: |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 28-nm HPC 0.9/1.8 V Databook (PHY Version: 2.60b) ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_28HPC18_x1 |
Product Code: |
A587-0 |
| |
Description: |
USB 3.0 PHY - TSMC 28HPC25 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_tsmc28hpc25_x1ns |
Version: |
3.02a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Change Bars (PHY Version 3.02a) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 28-nm HPC 0.9/2.5 V Databook (PHY Version: 3.02a) ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_28HPC25_x1 |
Product Code: |
A880-0 |
| |
Description: |
USB 3.0 PHY - TSMC 28HPL18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_tsmc28hpl_x1ns |
Version: |
2.2a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Change Bars (PHY Version 2.20a) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 28-nm HPL 1.0/1.8 V Databook (PHY Version: 2.20a) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_28HPL18_x1 |
Product Code: |
9845-0 |
| |
Description: |
USB 3.0 PHY - TSMC 28LP18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_tsmc28lp_x1ns |
Version: |
1.2a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 28-nm LP 1.05/1.8 V Databook (PHY Version: 1.20a) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_28LP18_x1 |
Product Code: |
A339-0 |
| |
Description: |
USB 3.0 PHY - TSMC 28LP25 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg_tsmc28lp25_x1ns |
Version: |
3.1a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 28-nm LP 1.05/2.5 V Databook (PHY Version: 3.10a) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_28LP25_x1 |
Product Code: |
7446-0 |
| |
Description: |
USB 3.0 PHY - TSMC 40G x1 |
Name: |
dwc_usb3phy_otg-tsmc40g-x1 |
Version: |
1.4a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
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Product Type: |
DesignWare Cores |
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Databooks DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 40-nm G 0.9/1.8 V Databook ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 PHY for TSMC 40-nm x1 G 0.9/1.8 V Databook With Change Bars (PHY Version: 1.40a) ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_40G18 |
Product Code: |
6904-0 |
| |
Description: |
USB 3.0 PHY - TSMC 40LP25 x1 |
Name: |
dwc_usb3phy_otg-tsmc40lp-x1 |
Version: |
2.8b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Change Bars (PHY Version 2.80b) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 40-nm LP 1.1/2.5 V Databook (PHY Version: 2.80b) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_40LP25 |
Product Code: |
8132-0 |
| |
Description: |
USB 3.0 PHY - TSMC 55LP25 x1 |
Name: |
dwc_usb3phy_otg-tsmc55lp-x1 |
Version: |
1.3a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
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DesignWare Cores |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks Current Databook With Changes (PHY Version: 1.30a) ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 55-nm LP 1.2/2.5 V Databook (PHY Version: 1.30a) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_55LP25 |
Product Code: |
9335-0 |
| |
Description: |
USB 3.0 PHY - TSMC 65LP x1 |
Name: |
dwc_usb3phy_otg-tsmc65lp-x1 |
Version: |
1.4b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
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DesignWare Cores |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks DesignWare Cores SuperSpeed USB 3.0 PHY One-Port for TSMC 65-nm LP/2.5 V Databook ( PDF )
DesignWare Cores SuperSpeed USB 3.0 PHY for TSMC 65-nm LP 1.2/2.5 V Databook ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 PHY for TSMC 65-nm x1 LP 1.2/2.5 V Databook With Change Bars (PHY Version:1.40b) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
DisplayLink Achieves First-Pass Silicon Success with Synopsys USB 3.0 IP ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
Fujitsu Semiconductor Selects Synopsys DigRFv4 M-PHY and DigRF 3G PHY IP for Customer's 2G/3G/4G Baseband Design ( PDF )
Realtek Achieves First Silicon Success for Industry's First Certified USB 3.0 Card Reader with Synopsys USB 3.0 IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_65LP |
Product Code: |
4937-0 |
| |
Description: |
USB 3.0 PHY - UMC 40LP25 x1 |
Name: |
dwc_usb3phy_otg_umc40lp_x1 |
Version: |
2.3.1a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks DesignWare® Cores SuperSpeed USB 3.0 PHY for UMC 40-nm LP 1.1/2.5 V Databook (PHY Version: 2.31a) ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 PHY for UMC 40-nm LP 1.1/2.5 V With Change Bars (PHY Version: 2.31a) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_UMC_40LP25 |
Product Code: |
9014-0 |
| |
Description: |
USB 3.0 PHY - UMC 65LL25 x1 |
Name: |
dwc_usb3phy_otg-umc65ll-x1 |
Version: |
1.1a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 PHY One-Port for UMC 65-nm LL/2.5 V Databook (PHY Version: 1.10a) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Evaluation Databook DesignWare Cores SuperSpeed USB 3.0 PHY One-Port for UMC 65-nm LL/2.5 V Evaluation Databook ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
DisplayLink Achieves First-Pass Silicon Success with Synopsys USB 3.0 IP ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
Fujitsu Semiconductor Selects Synopsys DigRFv4 M-PHY and DigRF 3G PHY IP for Customer's 2G/3G/4G Baseband Design ( PDF )
Realtek Achieves First Silicon Success for Industry's First Certified USB 3.0 Card Reader with Synopsys USB 3.0 IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_UMC_65LL25 |
Product Code: |
6834-0 |
| |
Description: |
USB 3.0 PHY, SMIC 40LL25 x1 |
Name: |
dwc_usb3phy_otg-smic40ll-x1 |
Version: |
2.05c |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare® Cores SuperSpeed USB 3.0 PHY for SMIC 40-nm LL 1.1/2.5 V Databook (PHY Version: 2.05c) ( HTML | PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Release Notes DesignWare® Cores SuperSpeed USB 3.0 PHY for SMIC 40-nm LL 1.1/2.5 V Release Notes (PHY Version: 2.05c) ( TXT )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
DisplayLink Achieves First-Pass Silicon Success with Synopsys USB 3.0 IP ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
Fujitsu Semiconductor Selects Synopsys DigRFv4 M-PHY and DigRF 3G PHY IP for Customer's 2G/3G/4G Baseband Design ( PDF )
Realtek Achieves First Silicon Success for Industry's First Certified USB 3.0 Card Reader with Synopsys USB 3.0 IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_SMIC_40LL25 |
Product Code: |
9308-0 |
| |
Description: |
USB 3.0 PHY-GF 28HPP18 x1 OTG, East/West poly orientation |
Name: |
dwc_usb3phy_otg_gf28hpp_x1ew |
Version: |
2.5a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks DesignWare® Cores SuperSpeed USB 3.0 PHY For GLOBALFOUNDRIES 28-nm HPP 0.85/1.8 V Databook (PHY Version: 2.50a) ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 PHY For GLOBALFOUNDRIES 28-nm HPP 0.85/1.8 V Databook With Change Bars (PHY Version: 2.50a) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_GF_28HPP18_x1EW_A |
Product Code: |
9862-0 |
| |
Description: |
USB 3.0 PHY-TSMC 28HPM18 x1 OTG, North/South Poly Orientation |
Name: |
dwc_usb3phy_otg-tsmc28hpm-x1ns |
Version: |
2.08a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks DesignWare® Cores SuperSpeed USB 3.0 PHY for TSMC 28-nm HPM 0.9/1.8 V Databook (PHY Version: 2.08a) ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 PHY for TSMC 28-nm HPM 0.9/1.8 V Databook With Change Bars (PHY Version: 2.08a) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
First-Pass Silicon Success for Myriad 2 Vision Processing Unit with Synopsys USB 3.0, LPDDR3/2 & MIPI D-PHY IP ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-PHY_TSMC_28HPM18_x1 |
Product Code: |
9258-0 |
| |
Description: |
USB 3.0 SSPHY - UMC 65LL x1 |
Name: |
dwc_usb3ssphy-umc65ll-x1 |
Version: |
1.6c |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SSPHY One-Port for UMC 65LL 1.2/2.5-V (Cypress) Process Technology Databook (PHY Version: 1.6c) ( PDF )
Datasheet Synopsys SuperSpeed USB 3.0 Complete Solution ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Virtualizing Cloud Computing With Optimized IP for NFV SoCs ( PDF )
|
Download: |
USB3-SSPHY_UMC_65LL |
Product Code: |
7349-0 |
| |
Description: |
USB 3.0 SSPHY, GF22FDSOI x1, North/South (vertical) poly orientation |
Name: |
dwc_usb3sspphy_gf22fdsoi_x1ns |
Version: |
3.05a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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DesignWare Cores |
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Databook DesignWare® Cores USB 3.0 SSPPHY for GF 22-nm FDSOI 0.8/1.8 V Databook (PHY Version: 3.05a) ( HTML | PDF )
Release Notes DesignWare® Cores USB 3.0 SSPPHY for GF 22-nm FDSOI 0.8/1.8 V Release Notes (PHY Version: 3.05a) ( TXT )
|
Download: |
USB3-SSPHY_GF_22FDX |
Product Code: |
C949-0 |
| |
Description: |
USB-C 3.0 femtoPHY, Type-C - TSMC 12FFC, North/South Poly Orientation |
Name: |
dwc_usbc3_femtophy_otg_tsmc12ffc_x1ns |
Version: |
4.02a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
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DesignWare Cores |
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Databook DesignWare Cores SuperSpeed USB 3.0 Type-C femtoPHY for TSMC 12-nm FFC 0./1.8 V Databook (PHY Version: 4.01a) ( PDF )
Release Notes DesignWare Cores SuperSpeed USB 3.0 Type-C femtoPHY for TSMC 12-nm FFC 0./1.8 V (PHY Version: 4.01a) ( TXT )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
dwc_usbc3_femtophy_otg_tsmc12ffc_x1ns |
Product Code: |
C645-0 |
| |
Description: |
USB-C 3.0 femtoPHY, Type-C - TSMC 16FF+LL, North/South Poly Orientation |
Name: |
dwc_usbc3_femtophy_otg_tsmc16ffpll_x1ns |
Version: |
4.01a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
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Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 Type-C femtoPHY for TSMC 16-nm FFPLL 0.8/1.8 V Databook (PHY Version: 4.01a) ( PDF )
Success Stories AMD Delivers Industry-Leading Ryzen and EPYC Processors with Synopsys DDR4, USB 3.0, PCIe 3.1, Ethernet & Foundation IP on 14-nm Process ( PDF )
AMD采用14纳米工艺,推出配有DesignWare DDR4、USB 3.0、PCIe 3.1、Ethernet and Foundation IP的行业领先的Ryzen和EPYC处理器 ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
USBC3-femtoPHY_TSMC_16FFPLL |
Product Code: |
C113-0 |
| |
Description: |
USB-C 3.0 femtoPHY, Type-C - TSMC 16FFC, North/South Poly Orientation |
Name: |
dwc_usbc3_femtophy_otg_tsmc16ffc_x1ns |
Version: |
4.01a |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databook DesignWare Cores SuperSpeed USB 3.0 Type-C femtoPHY for TSMC 16FFC 0.8/1.8 V Databook (PHY Version: 4.01a_d1) ( PDF | HTML )
Release Notes DesignWare Cores SuperSpeed USB 3.0 Type-C femtoPHY for TSMC 16FFC 0.8/1.8 V Release Notes (PHY Version: 4.01a) ( TXT )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
dwc_usbc3_femtophy_otg_tsmc16ffc_x1ns |
Product Code: |
C112-0 |
| |
Description: |
USB-C 3.0 femtoPHY, Type-C - TSMC 28HPC, North/South Poly Orientation |
Name: |
dwc_usbc3_femtophy_otg_tsmc28hpc_x1ns |
Version: |
4.01b |
ECCN: |
5E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML | PDF )
USB3 PHY Integration Review Checklist ( PDF )
Using the TIAO USB Multi-Purpose Adapter to Access JTAG on Synopsys IP ( PDF )
Databooks DesignWare Cores SuperSpeed USB 3.0 Type-C femtoPHY for TSMC 28-nm x1 HPC 0.9/1.8 V Databook (PHY Version: 4.01b) ( PDF )
DesignWare® Cores SuperSpeed USB 3.0 Type-C femtoPHY for TSMC 28-nm x1 HPC 0.9/1.8 V Databook With Change Bars (PHY Version: 4.01b) ( PDF )
White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF )
USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
|
Download: |
USBC3-femtoPHY_TSMC_28HPC |
Product Code: |
C114-0 |