- Silicon Design & Verification
- Silicon IP
- Software Integrity
- About Us
- Silicon Design & Verification Products
- Solutions
- Resources
- Services
- Community
- Training
- Silicon IP Products
- Solutions
- Resources
- Services
- Community
- Software Integrity
- Tools & Services
- Training & Education
- Solutions
- Resources
- Support
- Partners
- About Us
< Silicon Design & Verification Products
< Silicon Design & Verification Products
< Silicon Design & Verification Products
< Silicon Design & Verification Products
3D Image Processing
Simpleware Products
Simpleware for Life Sciences
Simpleware for Materials & Manufacturing
< Silicon Design & Verification Products
< Silicon Design & Verification Products
< overview
Silicon Design & Verification Products
+
Design
+
System Simulation & Modeling
+
Verification Continuum
+
3D Image Processing
+
Silicon Engineering
+
Optical Solutions
< Solutions
< Solutions
< Solutions
< Resources
< Resources
< Resources
< overview
< Services
< Services
< Services
< Community
Community
Community Overview
< Community
< Community
< Community
< Community
< Community
< Community
< Community
< overview
Community
+
Community
+
SNUG
+
Partners
+
EmbARC.org
+
Interoperability
+
Academic Programs
+
Company Blogs
+
BSIMM
< Training
< overview
< main menu
< Silicon IP Products
< Silicon IP Products
Memories & Libraries
Logic Libraries
Memory Compliers
Duet Packages
HPC Design Kit
Embedded Test & Repair
Non-Volatile Memory
< Silicon IP Products
< Silicon IP Products
Processor Solutions
ARC Processor IP
Embedded Vision Processor IP
Development Tools
Operating Systems
Ecosystem
ASIP Tools
< Silicon IP Products
< Silicon IP Products
< Silicon IP Products
< Silicon IP Products
< Silicon IP Products
< overview
Silicon IP Products
+
Interface IP
+
Memories & Libraries
+
Analog IP
+
Processor Solutions
+
IP Subsystems
+
Security IP
+
Market Segments
+
IP Accelerated
+
SoC Infrastructure IP
< Solutions
< Resources
< Services
< Services
< Services
< Community
Community
Community Overview
< Community
< Community
< Community
< Community
< Community
< Community
< Community
< overview
Community
+
Community
+
SNUG
+
Partners
+
EmbARC.org
+
Interoperability
+
Academic Programs
+
Company Blogs
+
BSIMM
< overview
Software Integrity
< Tools & Services
< Tools & Services
Professional Services
Strategy and Planning (BSIMM)
Architecture & Design
DevSecOps Integration
Cloud Security
Industry Solutions
< Tools & Services
Open Source Audits
< overview
< Training & Education
< Training & Education
Product Education
< overview
< Solutions
< Solutions
< Resources
< Resources
< Support
< Support
Contact Support
< Partners
< main menu
Software Integrity
+
Software Integrity
+
Tools & Services
+
Training & Education
+
Solutions
+
Resources
+
Support
+
Partners
< About Us
< About Us
< About Us
< About Us
< About Us
< About Us
DesignWare USB 2.0 Digital Controller IP
Synopsys provides designers with silicon-proven, configurable DesignWare® USB 2.0 Controllers that are compliant with the USB-Implementers Forum (USB-IF) USB 2.0 specifications. The DesignWare digital controllers provide: the lowest gate count; power management optimized with dual power rails; and a ULPI interface for discrete PHYs and UTMI/UTMI+ interface for integrated PHYs. This comprehensive solution includes the USB 2.0 LPM-HSIC, OTG, Host and Device Controllers.
The DesignWare USB 2.0 IP is the most certified IP solution in the industry. With thousands of design wins and billions of silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHY and Verification IP, enables designers to lower integration risk and speed time-to-market.
Synopsys optimized the USB 2.0 Controllers for low power, small area and ease-of-integration, such as is required in Internet of Things (IoT) applications.
DesignWare IP Prototyping Kit for USB 2.0 HS OTG DesignWare IP Prototyping Kits DesignWare USB 2.0 Controller IP DesignWare USB Link Power Management and High Speed Inter-Chip Datasheet
Highlights
Products
Downloads and Documentation
- Configuration options to maximize performance and minimize CPU interrupts
- Flexible parameters enable easy integration into low and high-latency systems
- Transfer- or transaction-based processing of USB data based on system requirements
- Configurable data buffering options to fine-tune performance/ area trade-offs
- Buffer and descriptor pre-fetching maximizes host throughput
- Firmware-selectable endpoint configurations enable post-silicon application changes and the flexibility of one-chip design for multiple applications
- Quality IP is tested through extensive Constrained Random Verification
- AMBA™ High-Performance Bus (AHB) interface enables rapid integration into ARM-based designs
- UTMI+ Level 3 enables rapid integration with compatible PHYs
- Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low- Speed (1.5 Mbps) operation is compliant to the USB OTG Supplement
- The USB 2.0 HS OTG Controller operates as either peripheral or host
- The Hi-Speed USB EHCI Host Controller is also available
| USB 2.0 Device Controller | STARs | Subscribe |
| USB 2.0 Device Controller version 4 with Active Clock Gating to save active power | STARs | Subscribe |
| USB 2.0 Host Controller Subsystem w/ PCI-AHB Interface Supporting HSIC | STARs | Subscribe |
| USB 2.0 Hi-Speed OTG Linux Software | STARs | Subscribe |
| USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only) | STARs | Subscribe |
| USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power | STARs | Subscribe |
| USB LPM-HSIC PHY - TSMC 65LP | STARs | Subscribe |