Synopsys provides designers with silicon-proven, configurable DesignWare® USB 2.0 Controllers that are compliant with the USB-Implementers Forum (USB-IF) USB 2.0 specifications. The DesignWare digital controllers provide: the lowest gate count; power management optimized with dual power rails; and a ULPI interface for discrete PHYs and UTMI/UTMI+ interface for integrated PHYs. This comprehensive solution includes the USB 2.0 LPM-HSIC, OTG, Host and Device Controllers.
The DesignWare USB 2.0 IP is the most certified IP solution in the industry. With thousands of design wins and billions of silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHY and Verification IP, enables designers to lower integration risk and speed time-to-market.
Synopsys optimized the USB 2.0 Controllers for low power, small area and ease-of-integration, such as is required in Internet of Things (IoT) applications.
DesignWare IP Prototyping Kit for USB 2.0 HS OTG
DesignWare USB 2.0 Controller IP
DesignWare USB Link Power Management and High Speed Inter-Chip Datasheet
Highlights
Products
Downloads and Documentation
- Configuration options to maximize performance and minimize CPU interrupts
- Flexible parameters enable easy integration into low and high-latency systems
- Transfer- or transaction-based processing of USB data based on system requirements
- Configurable data buffering options to fine-tune performance/ area trade-offs
- Buffer and descriptor pre-fetching maximizes host throughput
- Firmware-selectable endpoint configurations enable post-silicon application changes and the flexibility of one-chip design for multiple applications
- Quality IP is tested through extensive Constrained Random Verification
- AMBA™ High-Performance Bus (AHB) interface enables rapid integration into ARM-based designs
- UTMI+ Level 3 enables rapid integration with compatible PHYs
- Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low- Speed (1.5 Mbps) operation is compliant to the USB OTG Supplement
- The USB 2.0 HS OTG Controller operates as either peripheral or host
- The Hi-Speed USB EHCI Host Controller is also available
| USB 2.0 Device Controller | STARs |
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| USB 2.0 Device Controller version 4 with Active Clock Gating to save active power | STARs |
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| USB 2.0 Host Controller Subsystem w/ PCI-AHB Interface Supporting HSIC | STARs |
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| USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only) | STARs |
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| USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power | STARs |
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| USB LPM-HSIC PHY - TSMC 65LP | STARs |
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| Description: |
USB 2.0 Device Controller |
| Name: |
dwc_usb2_device |
| Version: |
4.30a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
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| Product Type: |
DesignWare Cores |
| Documentation: |
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Databooks Designware Cores USB 2.0 Device Controller Databook (4.30a) ( HTML | PDF )
Designware Cores USB 2.0 Device Controller Databook - with Change Bars (4.30a) ( PDF )
Datasheet DesignWare USB 2.0 Controller IP ( PDF )
Installation Guide Designware Cores USB 2.0 Device Controller Installation Guide (4.30a) ( PDF )
Programming Guides Designware Cores USB 2.0 Device Controller Programming Guide (4.30a) ( HTML | PDF )
Designware Cores USB 2.0 Device Controller Programming Guide - with Change Bars … ( PDF )
Release Notes Designware Cores USB 2.0 Device Controller Release Notes (4.30a) ( PDF )
User Guides Designware Cores USB 2.0 Device Controller User Guide (4.30a) ( PDF | HTML )
Designware Cores USB 2.0 Device Controller User Guide - with Change Bars (4.30a) ( PDF )
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| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_usb2_device |
| Product Code: |
B535-0 |
| | |
| Description: |
USB 2.0 Device Controller version 4 with Active Clock Gating to save active power |
| Name: |
dwc_usb_2_0_device_v4 |
| Version: |
4.30a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
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Databooks Designware Cores USB 2.0 Device Controller Databook (4.30a) ( HTML | PDF )
Designware Cores USB 2.0 Device Controller Databook - with Change Bars (4.30a) ( PDF )
Datasheet DesignWare USB 2.0 Controller IP ( PDF )
Installation Guide Designware Cores USB 2.0 Device Controller Installation Guide (4.30a) ( PDF )
Programming Guides Designware Cores USB 2.0 Device Controller Programming Guide (4.30a) ( HTML | PDF )
Designware Cores USB 2.0 Device Controller Programming Guide - with Change Bars … ( PDF )
Release Notes Designware Cores USB 2.0 Device Controller Release Notes (4.30a) ( PDF )
User Guides Designware Cores USB 2.0 Device Controller User Guide (4.30a) ( PDF | HTML )
Designware Cores USB 2.0 Device Controller User Guide - with Change Bars (4.30a) ( PDF )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_usb2_device |
| Product Code: |
B854-0, B855-0, B856-0, C436-0 |
| | |
| Description: |
USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only) |
| Name: |
dwc_usb_2_0_hs_otg_subsystem-ahb |
| Version: |
4.30a |
| ECCN: |
EAR99/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
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Application Notes Integrating USB 2.0 Hi-Speed On-The-Go Controller and USB 2.0 femtoPHY Application Note ( PDF )
Databooks DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Databook (4.30a) ( PDF | HTML )
DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Databook with Change Bars (4.30a) ( PDF )
Datasheet DesignWare USB 2.0 Controller IP ( PDF )
Installation Guide DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Installation Guide (4.30a) ( PDF )
Programming Guides DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Programming Guide (4.30a) ( PDF | HTML )
DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Programming Guide with … ( PDF )
Release Notes DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Release Notes (4.30a) ( PDF )
Success Stories ChipWrights achieves first-pass silicon success and meets aggressive schedule with … ( PDF )
Combination of Tools, IP and Services Help Teradici Achieve First Silicon Success ( PDF )
DesignWare Hi-Speed USB 2.0 OTG PHY and Controller IP Shortens austriamicrosystems … ( PDF )
High Quality IP Saves Open-Silicon Three Months on Schedule ( PDF )
User Guides DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) User Guide (4.30a) ( PDF | HTML )
DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) User Guide with Change Bars … ( PDF )
White Paper Shrinking SoC Design Cycles Using DesignWare Intellectual Property ( PDF )
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| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_otg |
| Product Code: |
3884-0 |
| | |
| Description: |
USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power |
| Name: |
dwc_usb_2_0_hs_otg_v4 |
| Version: |
4.30a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes Integrating USB 2.0 Hi-Speed On-The-Go Controller and USB 2.0 femtoPHY Application Note ( PDF )
Databooks DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Databook (4.30a) ( PDF | HTML )
DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Databook with Change Bars (4.30a) ( PDF )
Datasheet DesignWare USB 2.0 Controller IP ( PDF )
Installation Guide DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Installation Guide (4.30a) ( PDF )
Programming Guides DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Programming Guide (4.30a) ( PDF | HTML )
DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Programming Guide with … ( PDF )
Release Notes DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Release Notes (4.30a) ( PDF )
User Guides DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) User Guide (4.30a) ( PDF | HTML )
DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) User Guide with Change Bars … ( PDF )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_otg |
| Product Code: |
C435-0 |
| | |
| Description: |
USB 2.0 Host Controller Subsystem w/ PCI-AHB Interface Supporting HSIC |
| Name: |
dwc_usb_2_0_host_subsystem-pci-ahb |
| Version: |
3.00a |
| ECCN: |
EAR99/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
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Databooks DesignWare Cores USB 1.1 OHCI Host Controller Family Databook ( PDF )
DesignWare Cores USB 2.0 Host-AHB Controller Databook ( PDF )
DesignWare Cores USB 2.0 Host-AHB/PCI-AHB Controllers STAR Report ( PDF )
Datasheet DesignWare USB 2.0 Controller IP ( PDF )
Doc Overview DesignWare Cores USB 2.0 Host-AHB Controller Documentation Overview ( PDF )
Installation Guide DesignWare Cores USB 2.0 Host-AHB Controller Installation Guide ( PDF )
Reference Manual DesignWare Cores USB 2.0 Host-AHB Controller Test Environment Databook ( PDF )
Release Notes DesignWare Cores USB 2.0 Host-AHB Controller Release Notes ( PDF )
User Guide DesignWare Cores USB 2.0 Host-AHB Controller User Guide ( PDF )
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| Toolsets: |
Qualified Toolsets |
| Download: |
USB2-Host_Sub-PCI_AHB |
| Product Code: |
3520-0 |
| | |
| Description: |
USB LPM-HSIC PHY - TSMC 65LP |
| Name: |
dwc_usb_lpm-hsic_phy-tsmc_65lp |
| Version: |
1.2a |
| ECCN: |
3D991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
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Application Notes DesignWare Cores HSIC PHY Integration Review Checklist Application Note ( PDF )
Datasheet DesignWare USB Link Power Management and High Speed Inter-Chip Datasheet ( PDF )
|
| Download: |
USB-LPM-HSIC-PHY_TSMC_65LP |
| Product Code: |
4696-0 |
