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Article Archives
Issue Q2-10
- Propelled by HDMI, the First 3D Devices Hit the Shelves
- DesignWare Mobile Storage Host Controller Core: Handling Timing Requirement for SD3.0 Cards
Issue Q1-10
- The DesignWare HDMI 1.4 IP Solutions Revolutionize Home Theatre Multimedia Devices
- Accelerate the Development of Mobile Device with New DesignWare MIPI IP
- Synopsys Introduces Industry's First SystemC SuperSpeed USB 3.0 TLM-2.0 Models
Issue Q3-09
- Choosing the Right Architecture for Analog-to-Digital Conversion in Wireless Broadband Communications AFEs
- New Features for DesignWare DDR3/DDR2 SDRAM Memory Controller IP
- DesignWare minPower Components Slash Power in Datapath Circuit
- MIPI: Driving Innovation in the Mobile Industry
Issue Q2-09
- Introducing the Hybrid Architecture for the DesignWare Interconnect Fabric for the AMBA 3 AXI protocol
- Synopsys Enables System Design Interoperability with System-Level Catalyst Program
- DesignWare DDR3/2 PHY
- Synopsys Releases DesignWare SATA IP for New SATA 6Gb/s Data Transfer Rate
- Getting to Market Early With SuperSpeed USB Virtual Platforms
Issue Q1-09
Issue Q3-08
- Connecting a Standard SRAM Device to an AMBA 3 AXI Subsystem Using the DesignWare Generic Slave
- How to Connect Your DesignWare USB 2.0 nanoPHY to Your DesignWare USB 2.0 OTG Controller
- DesignWare Verification IP Quickstart for AMBA 3 AXI: A New View into Documentation
Issue Q2-08
- PCI Express Switch Enumeration Using VMM-Based DesignWare Verification IP
- USB 2.0 IP with Link Power Management Extension
- Functional Coverage Techniques: Leveraging DesignWare Verification IP and VMM for Efficient Testbenches
Issue Q1-08
- Synopsys Enhances DesignWare IP for DDR2 and DDR3
- USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
- Know Your Protocol: A Verification IP Perspective
- DDR2/3 SDRAM Controller Options: Protocol or Memory Controller
- Building a Bridge from PCI Express to AMBA 3 AXI On-Chip Bus
- Latest DesignWare IP SolvNet Articles
Issue Q4-07
- Tradeoffs Between Combinational and Sequential Dividers
- Low Power Methodology Demystified: Insights into the LPMM
- Understanding the DesignWare USB 2.0 Host Controller's New Feature for OHCI Clocks
- PCI Express 2.0: Comparing 2.5-Gbps Solutions Versus 5.0-Gbps
Issue Q3-07
Issue Q2-07
- DDR2 SNUG Tutorial: DDR2-533 and Beyond with DesignWare Memory Interface IP
- An Introduction to Synopsys' New SATA AHCI Digital Core Solution
Issue Q1-07
- IP and TCP/UDP Checksum Offload Functionality and its Support in Synopsys' DesignWare Ethernet MAC 10/100/1000 - Universal Core
- New SolvNet articles on DW IIP, VIP and DW Cores featuring AMBA, PCI Express and more
- Updates to TSMC Nexsys Libraries for the 65-nm and 90-nm Process Technology
- DesignWare Introduces Port Monitor Verification IP for the AMBA 3 AXI Protocol
- DesignWare Verification IP adds native performance in VCS for Verilog-based Testbenches
Issue Nov 2006
- Using DW_ahb_dmac in an AXI Subsystem
- Connecting an AMBA 2.0 AHB Subsystem to an AMBA 3 AXI Subystem
- DesignWare Introduces the AMBA 3 AXI to APB3 Bridge and Fabric Synthesizable IP
- DesignWare Introduces Bi-Directional Command Support in Interconnect Fabric for AMBA 3 AXI