Building a Bridge from PCI Express to AMBA 3 AXI On-Chip Bus
PCI Express® was developed as the next generation interface to replace PCI®, PCI-X®, and AGP for computer expansion cards and graphics cards. It provides
better bandwidth performance and the lower manufacturing costs, has layered architecture, and is backward compatible to the previous PCI
software infrastructure and easy to use. AMBA is an industry standard which drives the high performance, enable high reusability
and high connectivity. The Synopsys DesignWare PCI Express IP solution provides an AXI Bridging capability for directly adding a PCI Express link to
an AXI system fabric. This can significantly reduce the time to design PCI Express into an AXI-based SOC. In this
paper, we will discuss the process of building a bridge from PCI Express to the industry-standard AMBA® 3 AXI™ on-chip bus.
PCI Express Architecture Basics
PCI Express is a serial, point-to-point interface. It comprises of four device types:
- The Root Complex initializes the PCI Express fabric and is usually tied to the microprocessor.
- The Switch routes data between multiple PCI Express ports.
- The Endpoint is the requestor or completer of PCI Express transactions and is in the end application. Generally, you will have more endpoints in your design than any other type.
- Finally, the bridge is just what the name implies. It bridges between PCI Express and other interfaces; like PCI.
All these devices are connected with links. PCI Express link consists of a number of lanes. A lane is a differential pair for unidirectional transmission in both directions.
PCI Express defines that you can have multiple lanes running in parallel in order to increase performance of the link between two
devices. Each of the lanes provides its own embedded clocking, which removes the line length matching that was required for the old PCI
interface. The current version of the PCI Express specification defines the maxim number of lanes to be 32 with a frequency of 2.5 and 5.0 Gb/s.
The PCI Express protocol is defined into multiple layers.
Figure 1. PCI Express Topology
- Mechanical, which define things like the connectors
- The Physical Layer. The Physical layer is broken into two portions, the logical layer and the electrical layer. There is also a specification available called the Physical Interface for PCI Express or “PIPE” that defines the interface between the PHY and the rest of the physical interface.
- The Data Link Layer
- The Transaction Layer
- And the Application Layer
AMBA Based Sub-system Basics
AMBA based sub-system typically consists of a high performance system interconnect bus. The typical components in AMBA sub-system are very similar to PCI system except a
component called DMA. DMA stands for direct memory access. AMBA system has a centralized DMA unit which can perform data movement between memories and IO devices. PCI system has DMA resides in most of the IO devices.
AXI has 5 channels: Two command channels for read and write, two data channels for read response data and write data, and one response channel for write. It has ID
associated with every transaction. Therefore it is an interconnect that provides a full flexibility of implementing different interconnect architectures like many switch fabric architectures.
Figure 2: AMBA Sub-system Toplogy
Synopsys Solution for PCI Express to AXI Bridge
Synopsys offers a complete PCI Express solution including digital cores, PHY IP and verification IP. The digital cores are configurable and scalable to meet multiple
application requirements and have user-friendly native application interfaces or AHB/AXI interface.
The Figure 3 shows the system level view of the DWC PCIe AXI core. The AXI Bridge Module acts as a bridge between the standard AXI interfaces and the Synopsys DesignWare PCIe
core native interfaces. The bridge interconnects the AXI interfaces within an AMBA-embedded system with a remote PCIe link, as either a root complex port, or as an endpoint port. The bridge supports up to
three AXI interfaces, one for an AXI master, one for an AXI slave, and one for DBI access to the native PCIe core. The AXI master interface enables a remote PCIe device to read and write to an AXI
slave connected to the AXI bridge. The AXI slave interface enables an AXI master to read and write through the AXI bridge to a remote PCIe device. The slave DBI interface enables an AXI master to read and
write to registers inside the native PCIe core, or the device-specific registers attached to the PCIe native core’s ELBI interface.
Figure 3: System Level View of the DWC PCIe AXI Core
PCI Express to AXI Bridge Architecture
The PCI Express to AXI Bridge provides an interface between the DesignWare PCI Express IP's native application interface and the AXI interconnect. It enables a remote PCIe device to be either an AXI
slave or an AXI master. The bridge contains AXI master and slave protocol handlers, internal slave and master control for generic request and response interfaces, a packet composer, and a packet
decomposer for response formation. The slave and master protocol handlers support the AXI protocol conversion between an AXI transfer and a generic transfer within the bridge. The slave and master
generic interface supports the conversion of an AXI transfer to a PCIe transaction. The packet composer and decomposer support the segmentation and reassembly of a PCIe transaction.
Since PCIe has different transaction types, the PCI Express to AXI bridge needs some special side band signals to provide information to
control or report the status of a specific transaction. With the side band signals, users also can define error mapping between PCI Express errors (UR, CA, CRS,
poisoned, and ECRC error) and AXI slave response errors (SLVERR and DECERR). The bridge design provides an address translation port in case AXI and PCIe have different address space mapping.
Figure 4: AXI Bridge Architecture
It's pretty complex to develop a bridge to PCI Express from your Syetem-on-Chip design. This requires a fair amount of knowledge of the PCI Express standard, and the
design can be tough. Using DesignWare PCI Express with AXI Interface IP makes your design task considerably easier. The DesignWare PCI Express IP is configurable, scalable, synthesizable, and is easily to be added into SoC designs.