Understanding the DesignWare USB 2.0 Host Controller's New Feature for OHCI Clocks
Ajay Kumar, Application Engineering Manager, DesignWare IP
The current version (2.91a and earlier), of the Synopsys DesignWare USB 2.0 Host controller IP includes built-in mechanisms to suspend idle ports.
In suspend mode, the EHCI controller in the USB 2.0 Host Controller IP has the capability to support turning off the clocks to save power. From this mode, wherein the clocks are turned off, the EHCI controller is capable of asynchronous wake up. It can resume from suspend mode with the clocks still turned off.
Although the OHCI controller also enters suspend mode on idle condition on the bus, the12 and 48 MHz clocks need to be running, in order to come out of suspend mode. Currently, if the 12 and 48MHz clocks are turned off, users need to implement their own logic to bring the core out of suspend mode.
In the upcoming 2.92a version of the DesignWare USB 2.0 Host Controller IP (scheduled to be released at the end of December 2007), Synopsys will introduce new logic in the core to ease this functionality. The OHCI Host Controller will provide power management capabilities to switch the 12 MHz and 48 MHz clocks on/off for power savings.
The two new I/Os for the OHCI clock control and the functionality of the added logic are described below:
New input signals added:
* app_start_clk_i: OHCI Clock control signal
Function: This is an asynchronous primary input to the host core. When the OHCI clocks are suspended, the system has to assert this signal to start the clocks (12 and 48MHz). This should be de-asserted after the clocks are started and before the host is suspended again. (Host is suspended means HCFS = SUSPEND or all the OHCI ports are suspended).
Active State: High
* ohci_susp_lgcy_i: OHCI Clock control signal
Note: This strap must be tied low if the OHCI 48/12 MHz clocks are to be suspended when the EHCI and OHCI controllers are not active.
Function: This is a static strap signal with the following functionality:
- When tied HIGH and the USB port is owned by OHCI, the signal utmi_suspend_o_n reflects the status of the USB port. (suspended vs. not suspended).
- When tied LOW and the USB port is owned by OHCI, then:
- utmi_suspend_o_n asserts (0) if all the OHCI ports are suspended, or if the OHCI is in global suspend state (HCFS=USBSUSOPEND).
- utmi_suspend_o_n deasserts (1) if any of the OHCI ports are not suspended and OHCI is not in global suspend.
The strap input ohci_susp_lgcy_i must be tied low for power management. If the strap is tied high, the USB 2.0 Host Controller IP maintains the backward compatibility to versions 2.91a and earlier. If the strap is tied high, the OHCI clocks should not be shut down.
Process for stopping the OHCI clocks:
To shut down the 12 MHz and 48 MHz clocks while the ohci_susp_lgcy_i is low, the OHCI software driver forces the USB Host Controller IP into USB SUSPEND state by writing to the HcControl.HCFS bits or puts all the OHCI ports into SUSPEND state if there is no transfer scheduled. In this state OHCI clocks can be turned off. In this state the ports owned by OHCI de-assert utmi_suspend_o_n. The application clock generation/gating (on/off) circuitry must monitor the utmi_fs_xver_own_o port along with the utmi_suspend_o_n. If all the utmi_suspend_o_n owned by this OHCI are asserted low, the application clock generation/gating (on/off) circuitry can switch off the 12 MHz and 48 MHz clocks to this OHCI Host.
Process for starting the OHCI clocks:
To start the clocks, one of the following two actions must occur:
❖ The application clock generation/gating (on/off) circuitry must assert the app_start_clk_i high.
❖ The USB device must initiate a remote wakeup event.
This de-asserts the utmi_suspend_o_n to high. The clock gating logic starts the 12 MHz and 48 MHz clocks. External clock generation/gating logic can reside within the UTMI/UTMI+ PHY. However, within the UTMI/ UTMI+ PHY there is no need for the application to monitor the utmi_suspend_o_n and utmi_fs_xcver_own_o ports since the PHY keeps track of these signal states. If external clock generation/gating logic is outside the PHY, then the application must monitor the utmi_suspend_o_n and utmi_fs_xcver_own_o ports.
❖ If the Synopsys DesignWare USB 2.0 nanoPHY is being used, there is a single 48 MHz clock from the PHY. The 12 MHz should be derived out of 48 MHz. The 48 MHz clock is shut down automatically if all the ports to the USB 2.0 nanoPHY (including those owned by EHCI) are suspended. There is no need to monitor the utmi_fs_xver_own_o in this configuration.
❖ If the system clock hclk_i must be shut off, then in addition to making sure that EHCI/OHCI Controllers can be stopped, the utmi_suspend_o_n from all the physical ports must be monitored with an external clock generation/gating logic (outside the core).
Note: Any register access to the OHCI core must occur only after the OHCI clocks are started.