DesignWare Technical Bulletin Article

DesignWare DDR3/2 PHY

Requirements for Implementing High Data Rates using Wire-Bond BGA Packaging

The Synopsys DesignWare® Cores DDR IP portfolio is a complete, silicon-proven, system-level IP interface solution for ASICs, ASSPs, System-on-Chip (SoC) and System-in-Package applications requiring high-performance DDR3/2 SDRAM interfaces operating up to 1600Mbps. The DesignWare DDR3/2 IP is ideal for systems that require the higher performance or lower power consumption of DDR3 while wishing to maintain backward compatibility with DDR2 for maximum design and system cost flexibility.

One of the greatest challenges in any SoC that utilizes one or more high speed DDR3 channels (e.g., above the maximum 1066Mbps data rate available with DDR2) is the association that the high speed parallel data channel brings to the packaging technology and PCB design. Wire bond packages are often preferred for their lower cost yet flip chip packaging offers higher performance from a signal integrity perspective due to the lower inductance in the chip connectivity. This paper outlines the impact packaging has on high speed DDR interfaces and presents the requirements that a SoC developer must undertake in order to implement a high speed DDR3 channel with an SoC using wire bond technology.

What Makes the DDR SDRAM Interface Sensitive to Package Choice?
Packaging decisions play a critical role in determining the success or failure of a DDR interface. Poor power delivery characteristics can lead to effects from simultaneously switching outputs (SSO) that slow down the circuitry and distort waveforms leading to timing margin erosion. This effect is highlighted in Figure 1 where the write data eye on the left shows the waveform with a minimum of SSO (only one data bit is switching, the remaining data bits are held at static levels) versus the write data eye on the right that shows all data bits switching concurrently representing the worst case SSO. The data signals shown in all of the data eyes in this paper were measured using the K28.5+ and K28.5- components of the compliance pattern defined for PCI-Express 2.0 that is designed to excite inter-symbol interference and jitter effects. The red trapezoid shown in each data eye presents the data eye width (valid logic levels) expressed in units of time based on clean transitions through VIL / VIH (ac) at the data eye opening and VIH / VIL (dc) at the data eye closing.

Figure 1: Minimum and Maximum SSO Effect on Data Eye Width in a DDR3 Interface Operating at
1066Mbps - Wire Bond (65nm PHY, 32-bit memory channel, single rank system, typical operating conditions)

Figure 1 demonstrates the classic SSO impact on a single-ended DDR interface. Using Synopsys DesignWare Cores DDR2/3-Lite PHY and controller IP as characterized in a 65nm process, as all data bits switch in the same direction, a rush of current is either sourced by the I/O power supply or sunk into ground. The inductance of the power supply bond wires converts this current into a voltage change (via the relationship V = L * dI/dt) such that the power and ground rails collapse closer together which effectively slows down the data edges. The end result is a narrower data eye under worst case SSO conditions that erodes setup and hold time timing margin.

DDR interfaces further highlight the impact of SSO since the DDR Controller/PHY in the SoC must launch the source synchronous data strobe out of phase with the data (also called "center aligned" since the DDR PHY must launch the data with the data strobe centered in the data eye). However, the DDR SDRAM launches the data and the data strobe in phase (also called "edge aligned" since the DDR SDRAM launches the data and the data strobe at the same time, leaving the DDR PHY responsible for phase shifting the data strobe into the center of the data eye before it is used for data capture within the DDR PHY) which makes the write operations susceptible to SSO impact whereas the read operations are largely immune to SSO impact. During writes from the controller/PHY on the SoC, data signals can be delayed by SSO effects but the 90 delayed data strobe transitions are much less impacted by the simultaneously switching data since the SSO event is effectively over by the time the data strobe is driven by the PHY (refer to Figure 2). This introduces pattern dependent data to strobe skew that that disrupts the ideal 90 phase relationship and erodes the system timing budget. Since reads launched by the DDR SDRAM are in phase (data and strobe are launched at the same time), the SSO delay affects the data and data strobe equally, introducing a minimum of skew.

Figure 2: Minimum and Maximum SSO Effect on Data to Data Strobe Timing in a DDR3 Interface Operating at
1066Mbps - Wire Bond (65nm PHY, 32-bit memory channel, single rank system, typical operating conditions)

In addition to the data eye narrowing highlighted in Figure 1, Figure 2 shows the effect of SSO on the data to data strobe timing relationship. Adding the data strobe traces in yellow on top of the blue data signals from Figure 1 yields the following observations (only one phase of the strobe is shown - the DDR3 data strobes are differential signals):
  • The scenario with minimum SSO achieves ideal setup and hold timing exceeding the DDR3 SDRAM requirements at 1066Mbps
  • Worst case SSO shortens the setup time and increases the hold time, effectively shifting the data eye such that the data strobes move out of their optimal location in the data eye
  • The noise in the I/O power supplies caused by the maximum SSO case is clearly shown in the yellow data strobe traces as the data transitions.
Note that the DDR3-1066 channel shown in Figures 1 and 2 is a robust channel that achieves positive timing budgets under all operating conditions. However, operating beyond 1066Mbps using wire bond packaging requires careful design at the entire system level.

The Role of Packaging
Electronic packaging serves a distinctly mechanical role. It enables the connections on a fine pitch semiconductor device to be transitioned and attached to wider pitch, easily manufactured printed circuit board. This transition region presents a complex signal and power integrity challenge to the system implementer: distribute clean power to the semiconductor devices while maintaining viable signals being output from and input to the circuit I/Os.

The practical reality is that the SoC package is one of the items most often subjected to cost pressures in the semiconductor industry. Most of these pressures concentrate on the power delivery paths in the package. Because of the expense of the silicon, the designer often seeks to reduce the number of pads assigned to power delivery. Concurrently, these same pressures point to using less expensive wire bond technology in lieu of more expensive, lower inductance flip chip.

Bond Wire vs. Flip Chip
Flip chip packages have significant signal integrity advantages over wire bond packages. Flip Chip packaging offers lower inductance paths for the power and ground connections, reducing noise on the power rails. There is also less crosstalk in the chip to package substrate connection since tiny bumps replace long wires. Because of the shorter connection, signals also see a more consistent impedance profile in flip chip. The benefit of flip chip for high speed DDR operation is highlighted in Figure 3 which compares to Figure 1 that featured wire bond packaging. However, in Figure 3, the data eyes are shown at 1600Mbps as contrasted to the 1066Mbps data eyes in Figures 1 and 2. Using Synopsys DesignWare Cores DDR3/2 PHY and controller IP as characterized in the same 65nm process used for Figures 1 and 2, notice how the SSO effects in Figure 3 are minimized via the lower power supply inductance, even at the 50% higher data rates as compared to Figure 1. Figure 4 highlights how the lower inductance in the I/O supply rails with the flip chip packaging results in lower supply rail noise and therefore there is less impact on the timing relationship between the data and the data strobes for the maximum SSO scenario as compared to Figure 2.

Figure 3: Minimum and Maximum SSO Effect on Data Eye Width in a DDR3 Interface Operating at
1600Mbps - Flip Chip (65nm PHY, 32-bit memory channel, single rank system, typical operating conditions)

Figure 4: Minimum and Maximum SSO Effect on Data to Data Strobe Timing in a DDR3 Interface Operating at
1600Mbps - Flip Chip (65nm PHY, 32-bit memory channel, single rank system, typical operating conditions)

Wire bond packages still own the prominent role in high data rate DDR applications, particularly for cost conscious consumer applications. DDR2 at 800 and 1066Mbps has been successfully implemented in many wire bond SoCs. Because of the significant cost savings associated with wire bond over flip chip packaging, there is a great incentive to push wire bond performance as far as it will go (e.g., up to 1333Mbps and beyond). Implementation of wire bond packages for SoC with a DDR interface at higher frequencies requires a signal integrity analysis for the specific memory interface, package and PCB environment. The final output of the signal integrity analysis is the various timing budgets associated with the read operations, write operations and address/command interface. Care must be taken to ensure that the timing budgets properly account for any features of the host DDR PHY that are designed specifically to enable high speed operation. For example, in the case of the DesignWare Cores DDR3/2 PHY IP, Synopsys includes PVT compensated per-bit deskew circuitry to offset unintended data to data or data to strobe skew (such as that caused by on-chip variation [OCV] effects) and low jitter PLLs to minimize the jitter in the clocks sent to the SDRAMs and in the data strobe signals.

Requirements for Implementing Wire-Bond BGA Packaging and PCBs at High Data Rates
The following are some basic requirements to be considered in the package and PCB designs of systems to support high speed data rates (e.g., DDR3-1333) using a host in wire-bond BGA packaging. This is not meant to be an exhaustive list, nor is it meant to preclude engineering ingenuity; rather it is presented as a list of some of the more important factors to consider. Further guidance for these requirements can be found in the packaging and PCB design application guides provided to licensed users of the Synopsys DDR3/2 SDRAM PHY IP products. Users designing this form of system configuration must be either highly knowledgeable in Signal Integrity analysis, or work with an experienced service provider, such as Synopsys, for Signal Integrity services.

  1. Maximum 2:1:1 Signal:Power:Ground ratio for SSTL I/O signal (VDDQ) and supply cells (VSSQ) on the die
  2. Minimum 4-layer package substrate with power and ground planes providing stable signal references
  3. Short bond wires for I/O power and ground to lower inductance
    1. VSSQ - less than 1.0mm, 0.7mm maximum recommended
    2. VDDQ - less than 1.5mm, 1.2mm maximum recommended
  4. Crosstalk must be minimized in the bond wire region. 3D modeling of the package should be performed to determine the best way to achieve appropriate isolation.
  5. Maintain low crosstalk between traces. Spacing between etch should be 3X the height of the etch above the reference plane.
  6. Avoid routing any traces over or near gaps in planes.
  7. Skew between signals should be kept to a maximum of 5 to 10ps within a byte lane.
  8. The number of vias connecting a power or ground plane to the balls should equal the number of connections from the package substrate to the power or ground pads on the silicon. This applies to all layers of the substrate.
    1. Vias should be dispersed about the package to avoid areas of high current concentration.
    2. Signal vias should be near the reference plane vias. This will minimize the size of current loops reducing crosstalk within the package.
  9. Make sure package self resonant frequency is not near the desired frequency of operation. The resonant frequency is determined primarily by the on die decoupling and the total inductance of the VDDQ/VSSQ supply loop.
  10. Build a robust decoupling network that can readily supply current over multiple decades of frequency
  11. Die, package, and PCB should be modeled extensively. At these frequencies, secondary effects become more important as they consume a larger portion of the timing budget. Modeling the interrelationship between signals and power currents and how they interact with the decoupling network will go a long way to achieving success at higher bit rates.
  12. Simulate, simulate, and simulate. Spice models should be used in place of IBIS models where possible to increase accuracy.
About DesignWare Cores
Synopsys provides a broad portfolio of digital and mixed signal IP cores for system-on-chip designs. As the leading provider of connectivity and analog IP, Synopsys delivers the industry's most complete solutions for widely used protocols such as USB, PCI Express, SATA, Ethernet and DDR/DDR2/DDR3. With high-quality, silicon-proven IP that has been implemented in a wide variety of applications, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP: