DesignWare Introduces the AMBA 3 AXI to APB3 Bridge and Fabric Synthesizable IP

The DW_axi_x2p is an AXI-to-APB bridge that allows the connection of an APB slave to AXI. APB components attached to the DW_axi_x2p can be either AMBA 2 APB or AMBA 3 APB-compliant. In other words, they can include either or both of the signals, pready and pslverr, added by the AMBA 3 APB protocol.

One side of the DW_axi_x2p is an AXI slave interface, which accepts reads and writes from an attached AXI master interface. The other side is an APB 3 master interface, which provides reads and writes to attached APB components. The DW_axi_x2p is a configurable component, allowing the IP integrator to optimize the IP to suit specific design requirements.

Features

The DW_axi_x2p supports the following features:

Translates AXI transactions into APB transfers
- Complies with AMBA 3 APB Protocol Specification, Rev. 1.0 and the ARM AMBA AXI Protocol, Rev. 1.0
- Provides a configuration option for AMBA 2 (APB) compatibility
- Accepts simultaneous read/write AXI transactions; passes all AXI transactions to APB to execute one APB transfer at a time
- Provides AXI-to-APB data congruity checks; automatically avoids APB writes with incompatible address alignment or write strobes
Provides for flexible address and data port configurations
- AXI data ports: 8, 16, 32, 64, 128, 256, or 512 bits wide
- APB data ports: 8, 16, or 32 bits wide
- AXI address ports: 32 or 64 bits
- APB address ports: 8,16, or 32 bits
- Supports byte-invariant endianness: little-endian and big-endian for AXI and little-endian only for APB.
Supports up to 16 AMBA 2 or AMBA 3 APB slaves
Supports single clock or two asynchronous clock domains
Buffers AXI transactions
- Buffers activity on all AXI channels, minimizing channel stalling on AXI control, data, and response
- Supports a wide range of user-selectable depths for command queues, response buffer, read data, and write data buffers