DesignWare Technical Bulletin Article

PCI Express 2.0: Comparing 2.5-Gbps Solutions Versus 5.0-Gbps

Doug Aida, Technical Writer, DesignWare IP

With the availability of revision 2.0 of the PCI Express (PCIe) base specification and its optional 5.0-Gbps data rate, the need for SerDes PHYs that support this speed have started to appear. While some applications might need a 5-Gbps SerDes PHY IP, a 2.5-Gbps solution might be more suitable for other applications.

When considering these two solutions, it is important to consider each solution's cost and power consumption versus the total bandwidth required. The cost tradeoff is in terms of package costs (wirebond versus flip-chip) and die area (while two 2.5-Gbps links might equal a single 5.0-Gbps link,the 2.5-Gbps links are wider and can lead to larger die sizes). Power consumption is simple to compare: a 5.0-Gbps link has three or more times the power consumption of a 2.5-Gbps link.

To illustrate this comparison, assume there is expressed interest in a PCIe 2.0 switch solution for a Very Large-Scale Integration (VLSI). The switch will have four downstream ports; two of them will be for a wireless application. For these two ports, up to 5.0 Gbps of wireless bandwidth is expected to be used. PCIe 5.0-Gbps applications have large power and area requirements for most applications; therefore, it is important to understand the tradeoffs. In addition, some differences between the two versions of the PCIe base specification are not obvious; for this reason you need to know the required bandwidth.

In the preceding case, there are two basic issues. First, 5.0 Gbps is much more bandwidth than any known wireless standard. All the currently proposed standards use much less than 5.0 Gbps - typically 0.5-Gbps. Second, if the real objective is to transmit 5.0 Gbps of wireless data, this requirement cannot be met with a single 5.0-Gbps PCIe link due to the 8-bit/10-bit encoding and the PCIe overhead. Due to the 8-bit/10-bit encoding, 5.0 Gbps translates to only 4.0 Gbps of raw throughput. Due to the PCIe overhead, a 5.0-Gbps link really achieves approximately 3.0-3.5 Gbps of maximum throughput. For 2.5-Gbps links, this value is approximately 1.6-1.8 Gbps. 

To achieve 5.0 Gbps of wireless bandwidth, at least 10 Gbps of PCIe bandwidth is required. An interesting point about 10-Gbps of PCIe bandwidth is that according to version 2.0 of the PCIe base specification, a two-lane link is now optional, which means that one can no longer guarantee that all PCs will support two lanes; therefore, four lanes must be supported. To achieve 10-Gbps, obviously four lanes of 2.5-Gbps SerDes will be used. However, with a 5.0-Gbps PHY, four 5.0-Gbps lanes are still required to support 10 Gbps of bandwidth. Obviously there are huge power and area savings in using a 2.5-Gbps solution, because even if the application requires only two 5.0-Gbps links, four 5.0-Gbps links must be built to guarantee interoperability.

For a 10-Gbps wireless application, a 2.5-Gbps PCIe solution is preferable, because this solution is much smaller, requires much less power, and is much cheaper to implement. A 2.5-Gbps complete PCIe 2.0 solution comprises a PCIe 2.0 2.5-Gbps PHY IP with a PCIe 2.0 digital controller IP and corresponding verification IP - creating a fully compliant PCIe 2.0 solution operating at 2.5 Gbps. By using a four-lane PCIe 2.5-Gbps PHY IP, the resultant PCIe solution is about 1/2 to 1/3 the area of a 5.0-Gbps PCIe solution. Additionally, the former solution will use about 1/3 to 1/6 the power of the 5.0-Gbps solution. Finally, a 2.5-Gbps PCIe 2.0 IP solution can be used in almost any wirebond package.

To provide a more complete perspective on this topic, a second example is a one-lane PCIe 2.5-Gbps PHY versus a one-lane 5.0-Gbps PHY. Normally, you would think that two-four 2.5-Gbps lanes are required to match the bandwidth of one 5.0-Gbps lane. However, to date, Synopsys is not aware of a requirement for any application that uses bandwidth greater than 2.5 Gbps but less than 5.0 Gbps. Theoretically, a SATA hard drive would be an example (3.0 Gbps versus 2.5 Gbps), but currently, no one is building a single-lane PCIe-to-SATA connection - it is always a dual or quad SATA connection, which again results in bandwidth greater than 5.0 Gbps. To date, for every one-lane application, a 2.5-Gbps PCIe PHY works just as well as a 5.0-Gbps PCIe PHY, and the advantage of a one-lane 2.5-Gbps PCIe PHY is that it consumes about 1/3 the power of a 5.0-Gbps PHY and is much smaller.

Finally, for a given application, multiple options can be discussed depending on the cost and power consumption of the solution and the total bandwidth required. For bandwidths of 10 Gbps or less, you should always use a 2.5-Gbps PHY; the 5.0-Gbps PHY is interesting, but not attractive except as a comparison point. For 20 Gbps, discuss both 2.5- and 5.0-Gbps PHYs. For bandwidths greater than 40 Gbps, only a 5.0-Gbps solution can be considered, because the maximum number of lanes a PC can support is 16.

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