Synopsys Enhances DesignWare IP for DDR2 and DDR3
Synopsys has released the DDR2/3-Lite protocol controller that is compatible with the DesignWare DDR2/3-Lite PHYs and our DesignWare DDR2/DDR PHYs. Synopsys has also released an update of the DDR2/DDR Memory Controller and a new a new release of the DDR2/3-Lite Memory Controller. All Synopsys hard DDR2/DDR or DDR2/3-Lite PHYs are now complemented by the choice of either a protocol controller or memory controller.
The DesignWare DDRn SDRAM Controller IP is delivered as RTL-based IP for the best fit into a customer tool flow and design methodologies. The Protocol Controller (PCTL) is a low-latency, high performance single port controller which converts host port memory requests into DDRn SDRAM transactions. The PCTL manages all DDRn protocol requirements and optimizes DDRn precharge/activate commands across all banks to maximize DDRn data bus utilization. The PCTL's lean design and high performance make it ideal for memory subsystems with unique scheduling or application bus requirements not satisfied by a general-purpose memory controller and can easily be integrated with custom-designed memory management units. The Memory Controller (MCTL) is a full-featured, general-purpose memory controller which converts host port memory requests into DDRn transactions. MCTL manages all DDRn protocol requirements such as bank precharge/activate, ODT, and refresh. It includes support for up to 32 host ports, flexible port arbitration, and advanced command reordering/scheduling to optimize DDRn data bus utilization.
DesignWare DDR2/3-Lite IP Cores are compatible with JEDEC standard DDR3 and DDR2 SDRAM memories with speeds up to 1066Mbps. These products are designed for customers who want an area optimized solution for DDR2 or DDR3 memory subsystems operating up to 1066Mbps. This 'Lite' solution is area and feature optimized DDR3/2 IP for customers that want to go to market with DDR2 interfaces up to 1066Mbps and also want an insurance policy against equivalent DDR3 devices becoming cheaper while their chip remains in the market or they want the power savings by using DDR3.
In addition to the DDRn controller IP, Synopsys has also released the DDR2/3-Lite PHY supporting TSMC65LP at data rates up to 1066Mbps.
For more information on our DesignWare DDRn IP, please visit us at DesignWare DDR Solutions