Latest DesignWare IP SolvNet Articles

• Information on nbw implementation
• DW_ahb_dmac Support for Defined-Length Bursts
• Using Decimals in Clock Periods for Simulation with DesignWare VIP
• URMI error encountered while simulating DesignWare IIP
• PCI Express 2.0: Comparing 2.5-Gbps Solutions Versus 5.0-Gbps Solutions
• How to Change the Memory BAR Size in PCIe-AHB Cores
• DWC SATA Host PIO programming guidelines
• DesignWare USB 2.0 OTG PHY Hard Macro Test Interface
• PCI Express Cores: How can you parameterize 2 separate instances of the core?
• DesignWare USB 2.0 Device Subsystem IP: Coming out suspend during soft-disconnect
• DesignWare USB 1.1/2.0 Device Subsystem IP: Overrun condition in Buffer-Filled mode
• Synthesiszing DesignWare DW_arb_rr arbiter
• Functional Issue with DesignWare Sequential Divider DW_div_seq
• Synthesizing DesignWare Datapath Functions