MIPI: Driving Innovation in the Mobile Industry
Christophe Berteau-Pavy, Product Marketing Manager, Synopsys Inc.
The recent years have seen an explosive growth in the cellular phone market and consumer electronics devices have become increasingly portable and "connected". With the growing popularity of social media web sites such as Facebook, Twitter and the ubiquity of streaming media sites such as Hulu, consumers are expecting connectivity anywhere, anytime and on any device. These forces are increasing system design complexity and blurring the lines between traditional cellular phones, smartphones, PDAs and other consumer electronic devices. Your phone is your camera, your camera can upload to Youtube and you can watch full length high definition movies on a device in the palm of your hand.
To help reduce some of these design challenges and continue enabling innovation, the industry has come together to form the Mobile Industry Processor Interface (MIPI) Alliance. Driven by industry leaders, the goal of the MIPI alliance is to specify and promote standard interfaces for the main building blocks of feature rich smartphones such as Camera Sensors, Display Drivers, RFICs, Image Processors, GPS, Audio, etc. By doing so, the alliance aims at reducing the number of proprietary interfaces, accelerating time to market for mobile device manufacturers and reducing industry fragmentation. Because of the already stated convergence between phones and other handheld consumer devices, these standard interfaces are also making their way outside of the standard mobile phone platforms.
Looking at MIPI for the first time, the number of components and interfaces involved can be somewhat confusing. The rest of this article will give a high level overview of the characteristics of the main MIPI defined components.
DigRF defines a low pin-count, low EMI, serial digital interface between the BaseBand IC and the RF IC or transceivers and provides an alternative to Analog I/Q interfaces. It not only provides a way to insure interoperability but also enables a much more efficient system level implementation. The board of the MIPI Alliance approved the DigRF v3.09.04 specification in 2008. This version of DigRF provides support for 3GPP 2.5G/3G and utilizes a DigRF specific PHY. Meanwhile, the MIPI Alliance is actively working on finalizing the next revision of the DigRF specification - DigRF V4. The latest V4 specification provides support for 3GPP 2.5G/3.5G systems, including LTE and Mobile WiMax. The physical implementation relies on the MIPI M-PHY (described below) and in its most basic implementation requires only 7 pins. A typical LTE Class 3 implementation with 2 Rx lanes and 1 Tx lane would only require 9 pins. For further flexibility and power reduction, the protocol accounts for flexible data rates and different power modes.
DSI (Display Serial Interface) defines a serial interface between the Baseband IC and peripherals such as active matrix display modules. Leveraging the MIPI D-PHY as the physical layer, the serial interface provides higher bandwidth, lower EMI and lower power with less pins than traditional interfaces. This is mostly achieved by serialization of pixel and command transmission as opposed to having a parallel data bus with additional control signals. The standard is lane scalable and provides the flexibility to support up to four lanes in order to accommodate different bandwidth requirements.
CSI-2 (Camera Serial Interface) defines a serial interface between the Baseband IC and Camera peripherals. Leveraging the MIPI D-PHY as the physical layer, the serial interface provides higher bandwidth lower EMI and lower power with less pins than traditional interfaces. Similarly to DSI, the CSI-2 specification leverages the D-PHY for the physical layer and offers scalability up to four lanes.
The D-PHY specification defines the current Physical Layer for CSI-2, DSI and UniPro interfaces. It is a source synchronous, multilane PHY using two wires per data lanes and two wires per clock lane. The specification allows for a scalable number of lanes with a minimum requirement of one clock lane and one data lane. The data lanes can be configured as either unidirectional or bidirectional and have a specified throughput from 80 Mbps to 1 Gbps.
The M-Phy specification is the next generation physical layer interface being defined by the MIPI Alliance. It is intended to provide higher bandwidth, longer range and additional power savings compared to the D-PHY and to be adopted in future evolutions of CSI and Unipro. It is already being integrated in the DigRF V4 specification (under development). It should also be noted that MIPI and JEDEC have entered into a formal agreement to use the MIPI M-PHY in JEDEC's Universal Flash Storage (UFS). The M-PHY is scalable in terms of data rate and number of lanes and also provides support for multiple standby and power saving modes.
UniPro is an acronym for Unified Protocol and is a generic high speed serial interface for chip to chip interconnect within a mobile device. Like other MIPI interfaces, UniPro aims at reducing pin count, power requirements and EMI while enabling interoperability. The protocol is application agnostic and supports different types of data traffic. The most current version of UniPro (v1.1) specification leverages the MIPI D-PHY for the implementation of the physical layer. Enabling up to 4 lanes in each direction the maximum data rate for UniPro 1.1 is 4Gbps. UniPro has a clearly defined long term roadmap which includes support for higher bandwidth, MIPI M-PHY for physical layer and device network capability.
SLIMbus is a low power two wire multi-drop interface optimized for constant rate data streams such as Audio. The multi-drop architecture addresses the limitations of existing digital audio interfaces such as I2S and PCM which are point-to-point connections and typically support a limited number of data channels. In contrast, SLIMbus can support multiple high quality audio, data and device control channels. From a physical implementation point of view, SLIMbus consists of a simple synchronous two wire bus with a bidirectional data line and a unidirectional clock line propagated through the system.
Synopsys is a MIPI Alliance contributor and has multiple MIPI IP in the DesignWare IP portfolio. For more information, please visit: www.synopsys.com/designware